Nexperia USA Inc. 74AUP1G04GM,132

Overview

74AUP1G04GM,132 from Nexperia is a single low-power CMOS inverter with Schmitt-trigger input, operating across 0.8 V to 3.6 V supply range, delivering propagation delay as low as 1.1 ns at 3.6 V (CL = 5 pF), ICC ≤ 1.4 μA max over –40 °C to +125 °C, and IOFF-enabled partial power-down protection. It serves as a noise-immune signal inversion stage in battery-powered sensor interfaces and level-shifting I/O buffers.

For engineers reviewing the 74AUP1G04GM,132 datasheet, 74AUP1G04GM,132 pinout, 74AUP1G04GM,132 application, or 74AUP1G04GM,132 equivalent, key selection criteria include its ultra-low static current, wide-VCC Schmitt-trigger hysteresis, IOFF leakage < ±0.75 μA during power-down, and XSON6 (SOT886) package compatibility with high-density PCB layouts.

Technical Context

This device implements a single unbuffered inverting logic gate with hysteresis on the input to tolerate slow-rising signals and reject noise-critical for interfacing with mechanical switches or analog-sourced digital inputs. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current in multi-rail systems.

The AUP family uses advanced silicon process optimization to achieve sub-1-μA ICC at 0.8 V while maintaining rail-to-rail output swing and consistent timing across voltage and temperature. Input thresholds scale with VCC (e.g., VIH = 0.65×VCC min at 1.4 V), enabling robust operation in mixed-voltage domains.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); 6 terminals; body size 1.0 mm × 1.45 mm × 0.5 mm; no leads; side-wettable flanks not present; thermal pad absent.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverter applications.

Compared with SN74LVC1G04DBVR and 74LVC1G14GW,125, the 74AUP1G04GM,132 uniquely combines ultra-low ICC, scalable VIH/VIL, and IOFF-making it the only option for battery-critical, noise-prone, and partial-power-down designs.

Availability

74AUP1G04GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power management, automotive body control modules, and IoT edge node level shifting requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G04GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, with leadership in logic, discrete, and MOSFET technologies serving automotive, industrial, and mobile markets.

The 74AUP logic family targets ultra-low-power portable and energy-sensitive applications, emphasizing sub-1-μA static current, wide-VCC operation, and robustness in thermally demanding environments.

FAQ

What is the maximum recommended load capacitance for stable 74AUP1G04GM,132 operation?

The device is fully characterized up to 30 pF load capacitance, with propagation delay specified at 5 pF, 10 pF, 15 pF, and 30 pF. Driving >30 pF may increase tpd beyond datasheet limits and raise dynamic power dissipation; for heavier loads, add a series resistor or buffer stage to maintain timing integrity and avoid overshoot.

Does the 74AUP1G04GM,132 support true bidirectional signal translation?

No-it is a unidirectional inverter with defined input (A) and output (Y) terminals. While overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC, the output cannot source/sink current into a higher-voltage domain. For bidirectional level shifting, dedicated translators like NXSL1T45 must be used instead.

How does the IOFF feature behave when VCC is ramping during power-up?

IOFF activates only when VCC falls within 0 V ± 0.2 V. During power-up, the output remains high-impedance until VCC exceeds ~0.4 V, then transitions to active drive once internal biasing stabilizes (~10 μs after VCC > 0.8 V). No external power-on reset is needed for safe sequencing.

Can the no-connect (n.c.) pins on the SOT886 package be grounded or left floating?

Both n.c. pins (terminals 2 and 5) are electrically isolated die pads with no internal connection. They must remain unconnected-neither grounded nor tied to any net-to prevent parasitic coupling, solder bridging, or thermal stress that could compromise package reliability or signal integrity.