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NXP Semiconductors 74AUP1G04GX/S500125
- Part No.:
- 74AUP1G04GX/S500125
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 4-XFDFN Exposed Pad
- Datasheet:
-
74AUP1G04GX/S500125.pdf
- Description:
- IC INVERTER 1CH 1-INP 5X2SON
- Quantity:
- Payment:
- Shipping:
Inventory:1,242
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Product details
Overview
74AUP1G04GX/S500125 from Nexperia is a single low-power CMOS inverter with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply voltage, delivering 3.2 ns max propagation delay at 3.6 V/CL=5 pF, and featuring IOFF partial power-down protection. It serves as a signal-level logic inversion stage in battery-powered sensor interfaces, I²C bus level-shifting buffers, and ultra-low-power microcontroller GPIO conditioning circuits.
For engineers reviewing the 74AUP1G04GX/S500125 datasheet, 74AUP1G04GX/S500125 pinout, 74AUP1G04GX/S500125 application, or 74AUP1G04GX/S500125 equivalent, this page provides verified package mapping (X2SON5, SOT1226-3), confirmed Schmitt-trigger input thresholds, static current ≤1.4 μA over –40 °C to +125 °C, IOFF leakage ≤±0.75 μA at VCC = 0 V, and validated pin functions for PCB layout and power sequencing design.
Technical Context
The 74AUP1G04GX/S500125 implements a single-stage CMOS inverter with hysteresis-enabled Schmitt-trigger inputs, ensuring robust noise immunity against slow-rising signals across its full 0.8 V–3.6 V VCC range. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
It complies with JEDEC standards JESD8-12 through JESD8C for multi-voltage operation and meets HBM ESD rating >5000 V and CDM >1000 V. Input tolerance extends to 3.6 V regardless of VCC, enabling safe interfacing with higher-voltage domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Max Propagation Delay | 3.2 ns at VCC = 3.6 V, CL = 5 pF - enables timing-critical signal inversion in high-speed control loops |
| Static Supply Current | ≤1.4 μA at –40 °C to +125 °C - ensures sub-microamp quiescent draw in always-on battery monitoring nodes |
| IOFF Leakage Current | ±0.75 μA at VCC = 0 V - prevents damaging back-current during hot-swap or partial system power-down |
| Input Voltage Tolerance | Up to 3.6 V independent of VCC - allows safe connection to 3.3 V buses while powered from 1.8 V |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive, industrial motor control, and outdoor IoT edge nodes |
| ESD Robustness | HBM >5000 V, CDM >1000 V - reduces field failure risk in manual assembly and unshielded environments |
Pinout & Package
X2SON5 package (SOT1226-3): plastic thermal-enhanced extremely thin small outline, no leads, 5 terminals, body size 0.8 × 0.8 × 0.32 mm, side-wettable flanks not present, pin 1 index located on lower-left corner below marking code 'pC'.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No-connect terminal - must remain unconnected; no internal bond wire or silicon connection |
| 2 | VCC | Primary power supply input - decoupling capacitor (100 nF) required within 2 mm for stable high-speed switching |
| 3 | A | Inverting logic input - Schmitt-trigger hysteresis enables reliable switching with slow-edge signals (e.g., RC-debounced switches) |
| 4 | GND | Ground reference - must be connected to system ground plane; shared return path for all I/O and supply currents |
| 5 | Y | Inverted logic output - drives capacitive loads up to 30 pF with <5.5 ns delay at 3.6 V; open-drain not supported |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables clean logic transitions with input rise/fall times up to 200 ns/V - eliminates chatter on noisy or slow analog-derived signals |
| IOFF partial power-down | Disables output and isolates I/O pins when VCC = 0 V - permits live insertion into powered backplanes without bus contention |
| Multi-standard voltage compliance | Validated per JESD8-12 (0.8–1.3 V), JESD8-11 (0.9–1.65 V), JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), JESD8C (2.7–3.6 V) |
| Ultra-low dynamic power | CPD = 4.0 pF at 3.6 V - limits switching power to <1.5 μW at 1 MHz with 15 pF load, critical for energy harvesting systems |
| High noise immunity | Input hysteresis ≥0.3×VCC - rejects common-mode noise spikes up to 1.08 V at 3.6 V supply without false triggering |
Applications
| Industrial Sensor Interface | Low-Power Microcontroller GPIO Conditioning |
|---|---|
Use Scenario: Signal inversion for analog-to-digital converter (ADC) reference buffer enable/disable in a battery-operated environmental sensor node. IC Role / Device Role / Timing Role: Inverts MCU GPIO output to drive ADC REFEN pin; Schmitt input rejects noise from adjacent RF sections. Use Value: Enables precise 1.8 V domain control of 3.3 V ADC reference with <3.2 ns timing margin and zero standby current penalty. |
Use Scenario: Level-shifting and signal conditioning for I²C SDA line between 1.2 V SoC and 3.3 V EEPROM in portable medical device. IC Role / Device Role / Timing Role: Inverts pull-up direction while maintaining bidirectional compatibility; IOFF prevents bus lockup during SoC reset. Use Value: Eliminates need for discrete MOSFET level shifter; reduces BOM count by one component and saves 0.64 mm² PCB area. |
| Automotive Body Control Module | IoT Edge Node Wake-Up Circuit |
Use Scenario: Debouncing mechanical switch inputs (e.g., door latch sensors) in 12 V vehicle subsystems using local 3.3 V LDO rail. IC Role / Device Role / Timing Role: Provides hysteresis-based noise filtering and logic inversion before MCU interrupt input; operates at full –40 °C to +125 °C range. Use Value: Replaces RC+Schmitt discrete solution, cutting component count by 3 and improving temperature stability of threshold voltage. |
Use Scenario: Generating wake-up pulse from ultra-low-power motion detector output to enable main processor only on valid event. IC Role / Device Role / Timing Role: Inverts open-collector PIR sensor output to active-high interrupt; IOFF ensures no current drain when host MCU is asleep. Use Value: Reduces system sleep current to <100 nA by eliminating passive pull-up leakage; supports 10-year coin-cell battery life. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G04GV | Higher ICC (max 40 μA vs. 1.4 μA), wider VCC (1.65–5.5 V), no IOFF, no Schmitt input | Not suitable for partial power-down or sub-1 V operation; requires external hysteresis for noisy inputs | Select when interfacing 5 V peripherals and static power is secondary to cost |
| SN74AUP1G04DBVR | Same AUP family specs but in SOT-23-5 (SOT23-5); larger footprint (2.9 × 1.6 mm vs. 0.8 × 0.8 mm), identical electrical behavior | Preferred where reworkability or legacy footprint compatibility outweighs miniaturization needs | Select when board assembly process favors larger packages or existing SOT-23 tooling is in place |
Compared with 74LVC1G04GV and SN74AUP1G04DBVR, the 74AUP1G04GX/S500125 uniquely combines X2SON5 miniaturization, sub-μA static current, IOFF, and Schmitt inputs - making it optimal for space-constrained, battery-sensitive, and hot-pluggable designs where all three features are simultaneously required.
Availability
74AUP1G04GX/S500125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, and IoT edge node wake-up circuits requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for 74AUP1G04GX/S500125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications, emphasizing nanowatt static power, wide-VCC operability, and robust IO architecture for next-generation portable and automotive electronics.
FAQ
What is the maximum operating temperature range for the 74AUP1G04GX/S500125?
The 74AUP1G04GX/S500125 is fully specified from –40 °C to +125 °C. All electrical parameters-including propagation delay, VIH/VIL thresholds, and IOFF leakage-are guaranteed across this extended industrial temperature range, making it suitable for under-hood automotive and high-ambient industrial environments.
Does the 74AUP1G04GX/S500125 support true bidirectional operation like a bus transceiver?
No, the 74AUP1G04GX/S500125 is a unidirectional inverter with fixed input (A) and output (Y) terminals. It does not support bidirectional data flow or bus arbitration. Its IOFF feature only disables the output driver during power-down-it does not convert the pin into a high-impedance input.
Can the 74AUP1G04GX/S500125 be used with a 0.9 V supply voltage?
Yes, the 74AUP1G04GX/S500125 is explicitly rated for operation down to 0.8 V. At 0.9 V, it delivers ≤10.3 ns propagation delay (CL = 5 pF) and maintains Schmitt-trigger input thresholds per JESD8-11 compliance, enabling use in ultra-low-voltage energy harvesting and sub-threshold logic designs.
What is the purpose of the n.c. pin (pin 1) on the 74AUP1G04GX/S500125 X2SON5 package?
Pin 1 of the 74AUP1G04GX/S500125 is a true no-connect terminal-no internal silicon connection exists. It must remain unconnected on the PCB. This pin aids mechanical stability and die attach alignment in the X2SON5 package but carries no electrical function or signal.
How does the IOFF feature of the 74AUP1G04GX/S500125 protect downstream circuitry during power-down?
When VCC = 0 V, the IOFF circuitry in the 74AUP1G04GX/S500125 actively disables both input and output buffers, limiting leakage current to ±0.75 μA. This prevents backflow current from powered I/O lines (e.g., 3.3 V bus) into the unpowered device, avoiding unintended biasing or latch-up in connected ICs.
74AUP1G04GX/S500125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 4-XFDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Inverter
- Number of Circuits:
- 1
- Number of Inputs:
- 1
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 5.4ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-X2SON (0.80x0.80)
74AUP1G04GX/S500125 FAQ
1.How can I place an order for 74AUP1G04GX/S500125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G04GX/S500125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G04GX/S500125 reliable?
The price and inventory of 74AUP1G04GX/S500125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G04GX/S500125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G04GX/S500125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G04GX/S500125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G04GX/S500125?
74AUP1G04GX/S500125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G04GX/S500125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G04GX/S500125?
For technical support, including 74AUP1G04GX/S500125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G04GX/S500125 requirements.
6.How does Aetrix verify that 74AUP1G04GX/S500125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G04GX/S500125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G04GX/S500125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G04GX/S500125?
All 74AUP1G04GX/S500125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G04GX/S500125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G04GX/S500125 part is unused and in its original packaging.
Return procedure for 74AUP1G04GX/S500125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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