Nexperia USA Inc. 74AUP1G06GW,125

Overview

74AUP1G06GW,125 from Nexperia is a single low-power CMOS inverter with open-drain output and Schmitt-trigger input, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 0.9 μA (max), tpd ≤ 4.0 ns (VCC = 3.3 V, CL = 10 pF), and IOFF-enabled partial power-down protection for I²C bus buffering and level-shifting applications.

For engineers reviewing the 74AUP1G06GW,125 datasheet, 74AUP1G06GW,125 pinout, 74AUP1G06GW,125 application, or 74AUP1G06GW,125 equivalent, key selection criteria include open-drain drive capability, sub-1 μA static current, −40 °C to +125 °C operation, IOFF leakage < ±0.75 μA at VCC = 0 V, and TSSOP5 (SOT353-1) package compatibility with high-density PCB layouts.

Technical Context

This device implements a single-stage CMOS inverter with Schmitt-trigger hysteresis on the input (VIH/VIL thresholds vary with VCC), enabling robust noise immunity against slow-rising signals in mixed-voltage systems. Its open-drain output supports wired-AND logic, I²C pull-up interfacing, and bidirectional voltage translation.

The IOFF circuit actively disables output terminals when VCC = 0 V, preventing backflow current during partial power-down - a critical requirement for hot-swap and multi-rail subsystems. Input overvoltage tolerance up to 3.6 V allows safe interfacing with higher-voltage logic domains independent of VCC.

Key Specifications

Pinout & Package

TSSOP5 package (SOT353-1): plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverter-with-open-drain applications.

Compared with SN74LVC1G06DBVR and 74LVC1G07GW,125, the 74AUP1G06GW,125 uniquely combines sub-1 μA ICC, IOFF, and Schmitt input in a 0.8–3.6 V envelope - making it optimal for ultra-low-power, mixed-voltage, and hot-swap-sensitive applications where those three traits are simultaneously required.

Availability

74AUP1G06GW,125 is available at Aetrix Electronics and suitable for industrial sensor interface, I²C bus buffering, hot-swappable module control, and reset signal conditioning requiring stable component supply across automotive, industrial, and IoT product lifecycles.

Supply support for 74AUP1G06GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AUP (Advanced Ultra-low Power) family targets energy-constrained applications demanding nanowatt static power, wide VCC scalability, and robust IO features - designed specifically for battery-powered wearables, smart sensors, and modular industrial electronics.

FAQ

Can 74AUP1G06GW,125 drive a 10 kΩ pull-up to 3.3 V while maintaining VOL ≤ 0.4 V?

Yes. At VCC = 3.3 V and IO = 3.1 mA, VOL is guaranteed ≤ 0.45 V (−40 °C to +125 °C). With a 10 kΩ pull-up to 3.3 V, sink current is ~330 μA - well below the 4 mA test condition, ensuring VOL remains < 0.1 V in typical operation.

Does the Schmitt-trigger input require external hysteresis components?

No. Internal hysteresis is fully integrated: VIH − VIL ≥ 100 mV at VCC = 1.2 V and scales with supply voltage. This eliminates external resistors or comparators when cleaning up slow or noisy signals like reed switch closures or op-amp outputs.

Is pin 1 of 74AUP1G06GW,125 marked with a dot or notch?

Per Nexperia's marking specification (Table 2), the pin 1 indicator is located on the lower left corner of the device, below the "pR" marking code. The TSSOP5 package uses a molded index notch at the lead edge - not a dot - visible in the top view of Figure 6.

What is the maximum capacitive load the output can drive while staying within tpd spec?

The datasheet specifies tpd up to CL = 30 pF (e.g., 11.9 ns max at VCC = 3.3 V). Driving >30 pF increases propagation delay nonlinearly and may violate setup/hold timing in synchronous systems; for loads >30 pF, add a buffer stage or reduce trace length.