NXP Semiconductors 74AUP1G06GW-Q100125
- Part No.:
- 74AUP1G06GW-Q100125
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G06GW-Q100125.pdf
- Description:
- IC INVERTER 1CH 1-INP 5TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AUP1G06GW-Q100 from Nexperia is a single low-power CMOS inverter with open-drain output, Schmitt-trigger input, and IOFF partial power-down capability. It operates across 0.8 V to 3.6 V supply, delivers propagation delay as low as 0.8 ns at 3.0 V (CL = 5 pF), and supports automotive-grade temperature range (−40 °C to +125 °C). It is used in level-shifting, bus buffering, and I²C-compatible signal conditioning circuits.
For engineers reviewing the 74AUP1G06GW-Q100 datasheet, 74AUP1G06GW-Q100 pinout, 74AUP1G06GW-Q100 application, or 74AUP1G06GW-Q100 equivalent, key selection criteria include open-drain drive strength (4 mA sink at 3.0 V), ultra-low ICC (≤1.4 μA max), Schmitt-trigger hysteresis for noise immunity, and AEC-Q100 Grade 1 qualification for under-hood automotive use.
Technical Context
This device implements a single inverting logic gate with Schmitt-trigger input thresholds that vary by VCC (e.g., VIH = 0.75×VCC min at −40 °C to +125 °C), enabling robust operation with slow-rising signals. Its open-drain output supports wired-AND configurations and voltage-level translation between domains.
The IOFF circuit actively disables output leakage when VCC = 0 V, limiting IOFF to ±0.75 μA and preventing backflow current in partial power-down systems. Input overvoltage tolerance up to 3.6 V allows interfacing with higher-voltage controllers while powered from lower VCC rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Inverter with Schmitt-trigger input and open-drain output - enables noise-immune signal inversion and bus sharing via external pull-up. |
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Propagation Delay | 0.8 ns (min) to 4.0 ns (max) at VCC = 3.0 V, CL = 5 pF - ensures timing-critical compatibility in high-speed digital control loops. |
| Output Sink Current | 20 mA absolute max; 4.0 mA typical at VOL ≤ 0.50 V (VCC = 3.0 V) - sufficient to drive standard I²C bus loads and LED indicators. |
| Static Supply Current | ≤1.4 μA max at −40 °C to +125 °C - enables always-on monitoring nodes in battery-powered automotive modules. |
| AEC-Q100 Grade | Grade 1 (−40 °C to +125 °C) - qualified for engine control units, body electronics, and ADAS sensor interfaces. |
| ESD Robustness | HBM >5000 V, CDM >1000 V - withstands handling and system-level ESD events in manufacturing and field deployment. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, lead pitch 0.65 mm, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| n.c. | No-connect terminal | Internally unconnected; must be left floating or tied to GND per layout best practice - no electrical function. |
| A | Input | Schmitt-trigger inverter input; accepts 0.8 V–3.6 V logic levels; tolerant of slow edges (Δt/ΔV ≤ 200 ns/V). |
| GND | Ground reference | Primary 0 V return path for supply and signal; decoupling capacitor must be placed adjacent to this pin. |
| Y | Open-drain output | Active-low output requiring external pull-up; sinks up to 4 mA at VOL ≤ 0.50 V (VCC = 3.0 V). |
| VCC | Supply voltage | Core power rail (0.8–3.6 V); IOFF circuit monitors this pin to disable output during power-down. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger input | Provides ≥0.3×VCC hysteresis (e.g., 0.9 V at VCC = 3.0 V), rejecting noise on long traces or mechanical switch bounce. |
| IOFF partial power-down | Disables Y output and limits leakage to ±0.75 μA when VCC = 0 V - prevents backfeed in multi-rail systems like infotainment head units. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting - enables safe interfacing with 3.3 V microcontrollers while operating from 1.8 V supply. |
| Ultra-low dynamic power | CPD = 1.2 pF (VCC = 3.0–3.6 V) yields <1 μW dynamic dissipation at 1 MHz - critical for thermally constrained ECUs. |
| Automotive qualification | AEC-Q100 Grade 1 compliance verified per JESD22-A108, including 1000-cycle temperature cycling and HTOL stress testing. |
Applications
| Automotive Body Control Module | I²C Bus Level Translation |
|---|---|
Use Scenario: Signal conditioning for door lock actuator feedback lines exposed to EMI and voltage transients in vehicle chassis wiring. IC Role / Device Role / Timing Role: Inverter with Schmitt input cleans noisy switch signals before MCU GPIO sampling; open-drain output interfaces directly with 12 V pull-up networks. Use Value: Eliminates need for discrete RC filters and dual-supply translators; IOFF prevents backfeed into 3.3 V MCU domain during sleep mode. |
Use Scenario: Bridging 1.8 V sensor node I²C bus to 3.3 V master controller in ADAS camera module. IC Role / Device Role / Timing Role: Open-drain inverter acts as bidirectional level shifter for SDA/SCL lines, leveraging inherent I²C open-drain protocol compatibility. Use Value: Supports 400 kHz Fast-mode I²C with <4 ns propagation skew; Schmitt input rejects coupling noise from nearby high-current actuators. |
| Engine Coolant Temperature Monitoring | Smart Lighting Control Interface |
Use Scenario: Converting analog comparator output (from NTC-based temp sensing) into clean digital enable signal for radiator fan driver IC. IC Role / Device Role / Timing Role: Inverter provides precise threshold crossing detection with hysteresis; IOFF isolates fan driver during ECU reset sequences. Use Value: Reduces BOM count vs. op-amp + transistor solution; 0.8 V minimum VCC allows operation during cold-crank battery sag (≤6 V). |
Use Scenario: Driving PWM-dimmed LED strings in interior lighting where MCU GPIOs lack sufficient sink current. IC Role / Device Role / Timing Role: Open-drain output sinks LED current through external resistor; Schmitt input rejects PWM crosstalk from adjacent switching regulators. Use Value: Enables direct GPIO control without external MOSFET; 4 mA sink capability supports up to 3 parallel LEDs at 1.3 mA each (VCC = 3.3 V). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AUP1G06GZ-Q100 | XSON5 (SOT8065-1) package: 1.1 × 0.85 × 0.5 mm, side-wettable flanks, no leads - smaller footprint and enhanced thermal performance. | Preferred for space-constrained PCBs (e.g., radar sensor modules) where reflow inspection and thermal dissipation are critical. | Select GZ for automated optical inspection (AOI)-friendly layouts and improved power density; identical electrical specs and pinout. |
| SN74LVC1G06DBVRQ1 | TSSOP5 package but lacks Schmitt-trigger input; VIH/VIL fixed at 2.0 V/0.8 V (VCC = 3.3 V); IOFF not supported. | Suitable only for clean, fast-rising signals; cannot replace 74AUP1G06GW-Q100 in noisy environments or partial power-down systems. | Choose only if Schmitt input and IOFF are unnecessary; verify noise margin and power sequencing requirements first. |
Compared with 74AUP1G06GZ-Q100, the 74AUP1G06GW-Q100 offers identical logic behavior in a larger TSSOP5 package better suited for manual rework and thermal mass-sensitive applications; versus SN74LVC1G06DBVRQ1, it adds essential Schmitt noise immunity and IOFF for automotive power gating - making it irreplaceable in harsh or multi-rail systems.
Availability
74AUP1G06GW-Q100 is available at Aetrix Electronics and suitable for automotive body control, I²C level translation, and engine management systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G06GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance logic, analog, and discrete components, with core expertise in automotive-qualified silicon solutions.
The 74AUP1G06-Q100 belongs to Nexperia's AUP (Advanced Ultra-low Power) logic family, designed specifically for energy-efficient automotive subsystems requiring wide-VCC operation, robust noise immunity, and seamless integration into multi-voltage architectures.
FAQ
What is the maximum output sink current specification for the 74AUP1G06GW-Q100?
The 74AUP1G06GW-Q100 is rated for a maximum output sink current of 20 mA under absolute limiting conditions. In normal operation at VCC = 3.0 V, it guarantees VOL ≤ 0.50 V with IO = 4.0 mA, making it suitable for driving moderate-current loads such as I²C buses or indicator LEDs without external buffers. This value is validated across −40 °C to +125 °C.
Does the 74AUP1G06GW-Q100 support partial power-down via IOFF, and how does it behave when VCC = 0 V?
Yes, the 74AUP1G06GW-Q100 integrates IOFF circuitry that disables the output stage when VCC = 0 V. In this state, the Y pin enters high-impedance mode with power-off leakage current limited to ±0.75 μA (max), preventing damaging backflow current from other live rails. This behavior is specified and tested per JESD78 Class II latch-up standards.
Can the 74AUP1G06GW-Q100 be used with a 1.2 V supply, and what are the corresponding input threshold voltages?
Yes, the 74AUP1G06GW-Q100 operates down to 0.8 V VCC. At VCC = 1.2 V and ambient temperature −40 °C to +125 °C, VIH (min) = 0.70 × VCC = 0.84 V and VIL (max) = 0.30 × VCC = 0.36 V, providing 0.48 V of hysteresis. These Schmitt-trigger thresholds ensure reliable switching even with slow or noisy 1.2 V signals from ultra-low-power MCUs.
Is the 74AUP1G06GW-Q100 pin-compatible with the 74AUP1G06GZ-Q100, and what are the physical differences?
Yes, the 74AUP1G06GW-Q100 and 74AUP1G06GZ-Q100 share identical pin numbering, electrical specifications, and functional behavior. The sole difference is package: GW uses TSSOP5 (SOT353-1, 1.25 mm body width), while GZ uses XSON5 (SOT8065-1, 1.1 × 0.85 × 0.5 mm with side-wettable flanks). No PCB redesign is needed for footprint interchangeability.
What AEC-Q100 stress tests has the 74AUP1G06GW-Q100 passed, and which grade does it meet?
The 74AUP1G06GW-Q100 is qualified to AEC-Q100 Grade 1, covering −40 °C to +125 °C operation. It has passed all required stress tests including 1000-cycle temperature cycling, unbiased high-temperature storage (1500 h at +150 °C), and high-temperature operating life (1000 h at +125 °C with VCC applied), as documented in Nexperia's certified test reports.
74AUP1G06GW-Q100125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Inverter
- Number of Circuits:
- 1
- Number of Inputs:
- 1
- Features:
- Open Drain
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- -, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 10.5ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G06GW-Q100125 FAQ
1.How can I place an order for 74AUP1G06GW-Q100125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G06GW-Q100125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G06GW-Q100125 reliable?
The price and inventory of 74AUP1G06GW-Q100125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G06GW-Q100125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G06GW-Q100125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G06GW-Q100125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G06GW-Q100125?
74AUP1G06GW-Q100125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G06GW-Q100125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G06GW-Q100125?
For technical support, including 74AUP1G06GW-Q100125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G06GW-Q100125 requirements.
6.How does Aetrix verify that 74AUP1G06GW-Q100125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G06GW-Q100125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G06GW-Q100125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G06GW-Q100125?
All 74AUP1G06GW-Q100125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G06GW-Q100125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G06GW-Q100125 part is unused and in its original packaging.
Return procedure for 74AUP1G06GW-Q100125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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