Nexperia USA Inc. 74AUP1G07GN,132

Overview

74AUP1G07GN,132 from NXP Semiconductors is a single non-inverting buffer with open-drain output, designed for 1.1–3.6 V supply operation, featuring 3.7 ns typical propagation delay at 3.3 V and ±20 mA output drive capability. It serves as a level-shifting interface driver in low-power I²C bus expansion and GPIO signal conditioning circuits.

For engineers reviewing the 74AUP1G07GN,132 datasheet, 74AUP1G07GN,132 pinout, 74AUP1G07GN,132 application, or 74AUP1G07GN,132 equivalent, key selection criteria include open-drain compatibility with pull-up networks, sub-1 µA static current at 3.3 V, and guaranteed operation down to 1.1 V for ultra-low-voltage microcontroller interfacing.

Technical Context

This device implements a CMOS-based Schmitt-trigger input stage followed by a single-stage open-drain NMOS output driver. It supports bidirectional voltage translation between 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without external level shifters.

The AUP (Advanced Ultra-low Power) family uses optimized gate oxide and threshold voltage tuning to achieve rail-to-rail input tolerance and <100 nA ICC at VCC = 3.3 V, enabling direct integration into battery-powered sensor nodes and wearables.

Key Specifications

Pinout & Package

Supplied in a 6-pin XSON6 (1.45 × 1.0 mm, 0.5 mm pitch) leadless package with wettable flanks for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar open-drain buffer applications.

Compared with SN74LVC1G07DBVR and 74LVC1G17GW,125, the 74AUP1G07GN,132 uniquely combines sub-1 µA quiescent current, 1.1 V operation, and Schmitt-triggered open-drain output - making it the only choice for energy-critical, multi-rail, bus-connected applications.

Availability

74AUP1G07GN,132 is available at Aetrix Electronics and suitable for I²C bus extension, low-power sensor interfacing, and GPIO expansion requiring stable component supply across automotive infotainment modules, industrial IoT edge nodes, and portable medical monitors.

Supply support for 74AUP1G07GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.

The 74AUP logic family targets ultra-low-power, multi-voltage interface applications in battery-operated and energy-harvesting systems, emphasizing minimal ICC, wide VCC tolerance, and robust noise immunity.

FAQ

Can 74AUP1G07GN,132 be used as a level shifter between 1.2 V and 3.3 V I²C lines?

Yes. Its input accepts voltages down to 1.1 V and its open-drain output can be pulled up to any voltage ≤3.6 V. When Y is pulled to 3.3 V and A driven by a 1.2 V MCU, the device correctly translates logic levels while preserving I²C bus arbitration and clock stretching behavior.

Does this device require external pull-up resistors on the output?

Yes. The Y pin is an open-drain NMOS output with no internal pull-up. A single external resistor (typically 4.7 kΩ for 3.3 V I²C) must connect Y to the target bus voltage rail to establish HIGH logic level and ensure proper bus idle state.

What is the maximum capacitive load this buffer can drive reliably?

At VCC = 3.3 V, the device maintains ≤9.5 ns tpd driving up to 50 pF load capacitance. For loads exceeding 50 pF, propagation delay increases linearly - e.g., 15 ns at 100 pF - which may violate timing budgets in high-speed I²C fast-mode (400 kHz) or standard-mode (100 kHz) designs.

Is the 74AUP1G07GN,132 compatible with hot-swap insertion into a live system?

Yes. Its IOFF specification guarantees that input and output leakage remains below ±0.1 µA when VCC = 0 V, preventing back-driving of powered circuitry. This allows safe insertion into a live 3.3 V I²C bus provided the device's VCC is ramped after mechanical connection.