NXP Semiconductors 74AUP1G07GS,132
- Part No.:
- 74AUP1G07GS,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G07GS,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP1G07GS,132 from Nexperia is a single low-power CMOS buffer with open-drain output and Schmitt-trigger input, operating across 0.8 V to 3.6 V supply. It delivers ICC ≤ 1.4 μA max at −40 °C to +125 °C, supports IOFF partial power-down, and features overvoltage-tolerant inputs up to 3.6 V. Used in I²C bus level translation, GPIO expansion, and wired-AND logic interfaces where ultra-low static power and noise immunity are critical.
For engineers reviewing the 74AUP1G07GS,132 datasheet, 74AUP1G07GS,132 pinout, 74AUP1G07GS,132 application, or 74AUP1G07GS,132 equivalent, this device is selected for battery-powered sensor nodes, wearables, and industrial control I/O conditioning where sub-μA quiescent current, wide-VCC compatibility, and robust input hysteresis are mandatory design requirements.
Technical Context
The 74AUP1G07GS,132 implements a non-inverting buffer stage with open-drain output, requiring an external pull-up resistor to define high-level logic voltage. Its Schmitt-trigger input provides ≥0.3×VCC hysteresis (e.g., 0.9 V at VCC = 3.0 V), enabling reliable operation with slow-rising signals such as RC-debounced switches or long PCB traces.
IOFF circuitry actively disables the output when VCC = 0 V, limiting backflow current to ±0.75 μA max and preventing unintended power rail coupling during hot-swap or partial system shutdown-critical for multi-rail embedded systems with staggered power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| ICC (max) | 1.4 μA at −40 °C to +125 °C - ensures <1 μW static power at 1.8 V, extending battery life in always-on IoT endpoints. |
| VOL (max) | 0.50 V at IO = 4.0 mA, VCC = 3.0 V - guarantees clean LOW-state drive into standard 3.3 V I²C bus loads with 2.2 kΩ pull-up. |
| VIH/VIL Thresholds | VIH = 2.0 V min at VCC = 3.0 V; VIL = 0.9 V max - provides 1.1 V noise margin for 3.3 V systems, enhancing EMI resilience. |
| tpd (typ) | 2.2 ns at VCC = 3.3 V, CL = 5 pF - supports >100 MHz signal conditioning in timing-critical digital control paths. |
| ESD Rating | HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in handheld and field-deployable equipment. |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive modules, motor drives, and industrial PLC I/O stages. |
Pinout & Package
XSON6 package (SOT1202): plastic extremely thin small outline, no leads, 6 terminals, body size 1.0 × 1.0 × 0.35 mm. Pin 1 index located on lower-left corner below marking code "pS".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No internal connection - electrically isolated; must be left floating or tied to GND for mechanical stability. |
| 2 | A | Data input with Schmitt-trigger hysteresis - accepts slow edges (≤200 ns/V) without oscillation or metastability. |
| 3 | GND | Ground reference - serves as return path for all internal logic and output sink current; requires low-impedance PCB plane. |
| 4 | Y | Open-drain output - sinks current only; requires external pull-up to define HIGH voltage; supports wired-AND and I²C bus sharing. |
| 5 | n.c. | No internal connection - electrically isolated; must be left floating or tied to GND for mechanical stability. |
| 6 | VCC | Power supply - supplies core logic and output driver; IOFF activates when VCC = 0 V to block backfeed current. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V - allows single BOM item across multiple voltage domains (e.g., 1.2 V SoC I/O, 3.3 V MCU peripherals). |
| IOFF partial power-down | ±0.75 μA max VCC = 0 V leakage - prevents back-current damage during board-level power sequencing or hot-plug events. |
| Schmitt-trigger input | ≥0.3×VCC hysteresis - rejects noise on long traces or mechanical switch bounce without external RC filtering. |
| Overvoltage-tolerant inputs | 3.6 V absolute max input - permits interfacing with higher-voltage peripherals (e.g., 3.3 V sensors) while powered from 1.8 V. |
| Ultra-low ICC | 1.4 μA max at +125 °C - reduces thermal load and extends runtime in energy-constrained edge devices. |
Applications
| Industrial Sensor Interface | I²C Bus Level Translation |
|---|---|
|
Use Scenario: Connecting 1.8 V microcontroller GPIO to 3.3 V analog sensor with open-collector alert output. IC Role / Device Role / Timing Role: Buffer isolates voltage domains and conditions noisy interrupt signals using Schmitt-trigger input. Use Value: Eliminates external level shifter IC and RC filter; reduces BOM count by 2 components while maintaining <100 ns response latency. |
Use Scenario: Extending I²C bus length beyond 1 m in factory automation PLC backplane with mixed-voltage slaves. IC Role / Device Role / Timing Role: Open-drain Y output enables wired-AND topology; Schmitt input rejects EMI-induced glitches on long traces. Use Value: Supports 400 kHz I²C Fast Mode with 2.2 kΩ pull-up at 3.3 V while consuming <0.5 μW static power per node. |
| Wearable Device Power Sequencing | Automotive Body Control Module I/O |
|
Use Scenario: Enabling/disabling 2.5 V display backlight via 1.2 V PMIC-controlled GPIO in smartwatch firmware. IC Role / Device Role / Timing Role: Acts as voltage-agnostic enable gate; IOFF blocks reverse current when display rail powers down first. Use Value: Prevents 2.5 V rail from back-feeding into 1.2 V domain during sleep mode, eliminating risk of PMIC latch-up. |
Use Scenario: Interfacing LIN transceiver fault flag (open-collector) to 3.3 V MCU GPIO in door module with 12 V battery supply. IC Role / Device Role / Timing Role: Provides ESD-hardened, temperature-stable signal conditioning between harsh automotive environment and digital logic. Use Value: Withstands −40 °C to +125 °C ambient and >5 kV HBM ESD without derating; reduces failure rate in field deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer with open-drain output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G07DBVR | Wider VCC (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt input | Requires external Schmitt buffer for noisy environments; unsuitable for partial power-down systems | Select when interfacing 5 V peripherals and ESD tolerance >8 kV HBM is required; avoid in battery-critical designs. |
| 74LVC1G17GW,125 | Same XSON6 package; Schmitt input; push-pull output (not open-drain); VCC = 1.65–5.5 V | Cannot perform wired-AND or I²C bus extension; incompatible with open-drain protocols | Choose only for pure signal conditioning where active HIGH/LOW drive is needed and bus sharing is unnecessary. |
Compared with SN74LVC1G07DBVR and 74LVC1G17GW,125, the 74AUP1G07GS,132 uniquely combines sub-μA ICC, IOFF, Schmitt input, and open-drain output in a 1.0 mm × 1.0 mm XSON6 package-making it the sole option for ultra-low-power, multi-rail, noise-prone I²C or GPIO expansion use cases.
Availability
74AUP1G07GS,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power sequencing, automotive body control modules, and I²C bus extension requiring stable component supply across extended temperature and low-power constraints.
Supply support for 74AUP1G07GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in mass-market electronics.
The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and thermally constrained applications, emphasizing sub-μA static current, wide-VCC operation, and enhanced noise immunity without sacrificing speed.
FAQ
What is the maximum allowable input voltage when VCC = 0 V?
The 74AUP1G07GS,132 supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC state. When VCC = 0 V, VI may reach 3.6 V safely due to internal clamping diodes and IOFF isolation-enabling hot-plug operation in modular systems where signal lines power up before supply rails.
Can the open-drain output drive a 10 kΩ pull-up to 5 V?
No. The output is rated for VO ≤ 3.6 V absolute maximum. Driving a 5 V pull-up risks exceeding the output voltage rating and damaging the Y terminal. Use only with pull-ups referenced to VCC or ≤3.6 V supplies; for 5 V bus interfacing, add an external level-shifting transistor stage.
How does the Schmitt-trigger input improve performance in noisy environments?
The Schmitt-trigger provides ≥0.3×VCC hysteresis (e.g., 0.9 V at 3.0 V), meaning the input switches HIGH at ~2.0 V and LOW at ~1.1 V. This 0.9 V window rejects noise spikes and slow-edge interference that would cause chatter or false triggering in standard CMOS inputs, eliminating need for external RC filters.
Is the n.c. pin on SOT1202 electrically isolated or internally bonded?
Pins 1 and 5 in the SOT1202 (XSON6) package are confirmed no-connect-no internal bond wire or silicon connection exists. They are mechanically present for package symmetry and thermal relief but must remain unconnected or tied to GND solely for PCB mechanical stability; routing signals to them causes undefined behavior.
74AUP1G07GS,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- -, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT1202 (1x1)
74AUP1G07GS,132 FAQ
1.How can I place an order for 74AUP1G07GS,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G07GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G07GS,132 reliable?
The price and inventory of 74AUP1G07GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G07GS,132 is usually 5 days.
3.What payment methods are accepted for 74AUP1G07GS,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G07GS,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G07GS,132?
74AUP1G07GS,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G07GS,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G07GS,132?
For technical support, including 74AUP1G07GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G07GS,132 requirements.
6.How does Aetrix verify that 74AUP1G07GS,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G07GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G07GS,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G07GS,132?
All 74AUP1G07GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G07GS,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G07GS,132 part is unused and in its original packaging.
Return procedure for 74AUP1G07GS,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G07GS,132 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

