Nexperia USA Inc. 74AUP1G07GW,125
- Part No.:
- 74AUP1G07GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G07GW,125.pdf
- Description:
- IC BUF NON-INVERT 3.6V 5TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:762
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Product details
Overview
74AUP1G07GW,125 from Nexperia is a single low-power CMOS buffer with Schmitt-trigger input and open-drain output, operating across 0.8 V to 3.6 V supply. It delivers ICC ≤ 0.9 μA max static current, supports partial power-down via IOFF circuitry, and ensures robust noise immunity with input thresholds scaling to VCC. It is used in level-shifting I²C bus interfaces and battery-powered sensor node signal conditioning.
For engineers reviewing the 74AUP1G07GW,125 datasheet, 74AUP1G07GW,125 pinout, 74AUP1G07GW,125 application, or 74AUP1G07GW,125 equivalent, key selection criteria include its 0.8–3.6 V wide VCC range, IOFF-enabled partial power-down capability, Schmitt-trigger hysteresis for slow-edge tolerance, and guaranteed operation from –40 °C to +125 °C.
Technical Context
This device implements a non-inverting buffer stage with hysteresis on the input (VIH/VIL thresholds scale with VCC), enabling reliable operation with slow-rising or noisy signals. Its open-drain output requires an external pull-up resistor and supports wired-AND logic and voltage-level translation between domains.
The IOFF circuit actively disables output leakage when VCC = 0 V, limiting backflow current to ±0.75 μA max - critical for hot-swap and multi-rail systems. Input overvoltage tolerance up to 3.6 V allows interfacing with higher-voltage logic without clamping diodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| ICC (max) | 0.9 μA at –40 °C to +125 °C - ensures ultra-low quiescent power in always-on IoT sensor nodes and wearables. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - prevents damaging back-current during power sequencing or partial system shutdown. |
| tpd (max) | 11.4 ns at VCC = 3.3 V, CL = 30 pF - supports reliable timing in sub-50 MHz digital control paths and status signaling. |
| Input Hysteresis | Typical ΔV = 0.1×VCC - rejects noise spikes and stabilizes output against slow transitions in industrial sensor inputs. |
| ESD Rating | HBM > 5000 V, CDM > 1000 V - meets IEC 61000-4-2 Level 4 requirements for board-level ESD robustness. |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive modules, industrial PLC I/O, and outdoor edge devices. |
Pinout & Package
TSSOP5 plastic thin shrink small outline package (SOT353-1); 5 leads; body width 1.25 mm; pin 1 indicator located below marking code in lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No internal connection - electrically isolated; no routing or grounding required. |
| 2 | A | Data input with Schmitt-trigger action - accepts slow or noisy signals; VIH/VIL scale with VCC. |
| 3 | GND | Ground reference (0 V) - must be low-impedance return path for all internal currents and IOFF control. |
| 4 | Y | Open-drain output - requires external pull-up; sinks up to 20 mA; supports wired-AND and level translation. |
| 5 | VCC | Supply voltage input - powers internal logic and enables IOFF circuitry; decoupling capacitor recommended. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V - eliminates need for separate voltage regulators in mixed-supply systems. |
| IOFF partial power-down | Active leakage control at VCC = 0 V - enables safe insertion/removal in live backplanes and modular systems. |
| Schmitt-trigger input | Hysteresis ≈ 0.1×VCC - suppresses chatter on mechanical switch inputs or long PCB traces. |
| Overvoltage-tolerant inputs | Withstands up to 3.6 V regardless of VCC - simplifies interfacing with legacy 5 V peripherals via resistive dividers. |
| Low-noise switching | Overshoot/undershoot < 10 % of VCC - reduces EMI in EMC-sensitive medical and automotive applications. |
Applications
| I²C Bus Level Shifter | Industrial Sensor Interface |
|---|---|
|
Use Scenario: Translating 1.8 V microcontroller I²C signals to 3.3 V peripheral side while maintaining bus integrity. IC Role / Device Role / Timing Role: Open-drain buffer acting as bidirectional level translator with Schmitt-trigger noise rejection on SDA/SCL lines. Use Value: Eliminates discrete MOSFET translators; supports 400 kHz Fast-mode I²C with <11.4 ns propagation delay and <10 % overshoot. |
Use Scenario: Conditioning push-button or limit-switch signals in programmable logic controllers with noisy 24 V DC field wiring. IC Role / Device Role / Timing Role: Input buffer with hysteresis converting slow, bouncing mechanical inputs into clean digital logic levels. Use Value: Reduces firmware debouncing overhead; operates reliably at –40 °C to +125 °C with ±0.75 μA IOFF leakage during controller sleep. |
| Battery-Powered Wearable Alert | Automotive Body Control Module |
|
Use Scenario: Driving a piezo buzzer from a 1.2 V coin-cell-powered MCU with minimal standby current draw. IC Role / Device Role / Timing Role: Low-VCC buffer enabling direct drive of buzzer via open-drain output and external pull-up to higher voltage rail. Use Value: Achieves 0.9 μA max ICC at 1.2 V - extends battery life beyond 2 years in intermittent-alert applications. |
Use Scenario: Isolating diagnostic LED driver signals from main MCU domain during ignition-off sleep mode. IC Role / Device Role / Timing Role: Signal isolator using IOFF to block reverse current when body control unit is powered down. Use Value: Prevents parasitic drain through LED circuits; certified for AEC-Q100 Grade 1 (–40 °C to +125 °C) operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer-with-open-drain-output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G07DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt input | Requires ≥1.65 V supply; unsuitable for sub-1.65 V systems or partial power-down designs | Choose only if interfacing with 5 V peripherals and full power is always available. |
| 74LVC1G07GW,125 | Same TSSOP5 package; higher ICC (10 μA max); no IOFF; VCC min = 1.65 V; no Schmitt input | Lacks hysteresis and power-down protection - vulnerable to noise and back-current in mixed-rail systems | Select only for cost-sensitive, non-critical 3.3 V-only applications where ultra-low power is not required. |
Compared with SN74LVC1G07DBVR and 74LVC1G07GW,125, the 74AUP1G07GW,125 uniquely combines sub-1 V operation, Schmitt-trigger noise immunity, and IOFF-enabled safe power sequencing - making it the sole choice for energy-constrained, multi-voltage, or automotive-grade signal conditioning.
Availability
74AUP1G07GW,125 is available at Aetrix Electronics and suitable for industrial sensor nodes, automotive body electronics, and battery-powered wearable interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G07GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line is engineered for energy-efficient signal conditioning in battery-operated and thermally constrained systems, emphasizing ultra-low ICC, wide VCC scalability, and robust IOFF behavior.
FAQ
Can 74AUP1G07GW,125 drive an LED directly?
No - its open-drain output can only sink current. To drive an LED, connect the anode to a positive supply (e.g., 3.3 V) and the cathode to Y, with a series current-limiting resistor. The device supports up to 20 mA sink current but does not source current from Y.
What is the purpose of the n.c. pin on the TSSOP5 package?
Pin 1 is internally unconnected and serves no electrical function. It must remain unconnected on the PCB - no routing, grounding, or termination is required. This pin exists solely for mechanical alignment and package symmetry.
Does the Schmitt-trigger input eliminate the need for external RC filtering?
It significantly reduces but does not eliminate the need for filtering. The hysteresis (≈0.1×VCC) rejects fast noise transients and contact bounce, yet sustained high-frequency interference (>10 MHz) or EFT bursts still require board-level RC or ferrite filtering per IEC 61000-4-4.
How does IOFF behave when VCC is ramping during power-up?
IOFF activates only when VCC falls to 0 V or near-zero (<0.2 V). During normal power-up, the device operates as a standard buffer. IOFF does not engage during brown-out or slow VCC ramps - it is strictly a zero-VCC protection feature.
74AUP1G07GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- -, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G07GW,125 FAQ
1.How can I place an order for 74AUP1G07GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G07GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G07GW,125 reliable?
The price and inventory of 74AUP1G07GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G07GW,125 is usually 5 days.
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Once your 74AUP1G07GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G07GW,125?
For technical support, including 74AUP1G07GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G07GW,125 requirements.
6.How does Aetrix verify that 74AUP1G07GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G07GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G07GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G07GW,125?
All 74AUP1G07GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G07GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G07GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G07GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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