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NXP Semiconductors 74AUP1G0832GM,115
- Part No.:
- 74AUP1G0832GM,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G0832GM,115.pdf
- Description:
- NEXPERIA 74AUP1G0832GM- AND-OR G
- Quantity:
- Payment:
- Shipping:
Inventory:86,193
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Product details
Overview
74AUP1G0832GM,115 from Nexperia is a single 3-input AND-OR logic gate (Y = (A × B) + C) with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering 0.9 μA max ICC at 125 °C and supporting partial power-down via IOFF circuitry. It enables robust signal conditioning in low-voltage battery-powered sensor interfaces and I/O expansion circuits.
For engineers reviewing the 74AUP1G0832GM,115 datasheet, 74AUP1G0832GM,115 pinout, 74AUP1G0832GM,115 application, or 74AUP1G0832GM,115 equivalent, this device is selected for ultra-low static power, overvoltage-tolerant 3.6 V inputs, and guaranteed operation across –40 °C to +125 °C in space-constrained XSON6 packages.
Technical Context
This device implements a fixed Boolean function Y = (A × B) + C using CMOS logic with Schmitt-trigger input thresholds-ensuring noise immunity against slow-rising signals and enabling reliable interfacing with mechanical switches or analog-sourced digital inputs. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
Designed for wide-VCC operation, it meets JEDEC standards JESD8-12 through JESD8-B across five voltage bands and achieves <10% VCC overshoot/undershoot. Propagation delay ranges from 1.3 ns (VCC = 3.6 V, CL = 5 pF) to 7.0 ns (VCC = 3.6 V, CL = 30 pF), with input capacitance of 0.8 pF and output capacitance of 1.7 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Y = (A × B) + C - enables conditional enable gating where two signals must both be HIGH to activate an OR path with a third independent input |
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains without level shifters |
| Max ICC (125 °C) | 0.9 μA - ensures sub-1 μA quiescent draw in always-on monitoring nodes |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging back-current during hot-swap or multi-rail sequencing |
| Propagation Delay (3.6 V, 5 pF) | 1.3–3.9 ns - provides timing predictability for high-speed control logic in portable MCU peripherals |
| Input Threshold Hysteresis | Schmitt-trigger action - eliminates chatter on noisy or slow edges from encoders, pushbuttons, or analog comparators |
| ESD Rating (HBM) | 5000 V - withstands handling and board-level ESD events without protection diodes |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; thermal pad optional; pin 1 index located at lower-left corner below marking code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data input A | First AND operand in Y = (A × B) + C; Schmitt-triggered for noise rejection |
| GND | Ground reference | 0 V return path for logic and IOFF circuitry; must be low-impedance for stable threshold behavior |
| B | Data input B | Second AND operand; electrically identical to A with same VIH/VIL hysteresis |
| Y | Data output Y | Open-drain–compatible CMOS output driving up to ±4 mA at 3.0 V; rail-to-rail swing |
| VCC | Supply voltage | Primary power rail (0.8–3.6 V); powers internal logic and IOFF control block |
| C | Data input C | Direct OR operand - bypasses AND stage; enables priority override or fault signaling |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | 0.9 μA max ICC across full temperature range enables decade-long battery life in IoT wake-up logic |
| IOFF partial power-down | Blocks bidirectional current flow when VCC = 0 V, allowing safe insertion into live backplanes |
| Schmitt-trigger inputs | Guaranteed hysteresis across all VCC levels eliminates metastability from slow transitions in industrial sensors |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting - simplifies mixed-voltage interconnect without external clamps |
| Wide temperature range | Specified from –40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives |
Applications
| Industrial Sensor Interface | Portable Device Power Sequencing |
|---|---|
Use Scenario: Conditioning switch bounce and EMI noise from limit switches in PLC I/O modules. IC Role / Device Role / Timing Role: Logic gate performing debounced AND-OR combination to trigger safety cutoff only when dual sensors agree, plus manual override. Use Value: Eliminates need for external RC filters or microcontroller polling, reducing BOM count and firmware complexity. | Use Scenario: Enabling subsystem power rails only after primary regulator stabilizes and thermal sensor reads safe. IC Role / Device Role / Timing Role: Combines enable signals from voltage monitor (A), thermal flag (B), and reset timeout (C) to gate downstream LDO activation. Use Value: Ensures fail-safe power-up sequence with hardware-level redundancy - no software dependency or boot-time race conditions. |
| IoT Edge Node Wake-Up Logic | Automotive Body Control Module |
Use Scenario: Aggregating motion, light, and proximity interrupts to wake an MCU from deep sleep. IC Role / Device Role / Timing Role: OR-ing ambient event triggers (C) while AND-ing motion+light (A×B) to suppress false wakes from transient noise. Use Value: Reduces average current by >95% versus always-on GPIO monitoring, extending coin-cell lifetime beyond 5 years. | Use Scenario: Controlling LED driver enable based on ignition status, door latch, and CAN bus activity. IC Role / Device Role / Timing Role: Gate combining ignition ON (A), door open (B), and CAN activity pulse (C) to drive interior lighting logic. Use Value: Provides deterministic, glitch-free enable timing independent of CAN message latency or MCU boot state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-input AND-OR logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G57GW,125 | Configurable多功能 gate (multiple logic functions via select pins); higher ICC (4 μA typ); no IOFF | Requires configuration pins and external pull-ups; unsuitable for hot-swap or multi-rail isolation | Select when flexibility across AND/OR/XOR is needed and power-down isolation is not required |
| SN74AUP1G57DBVR | Same logic function and IOFF; larger SOT-23-6 package (2.9 × 1.6 mm); 1.5× higher propagation delay at 1.8 V | Less suitable for ultra-dense layouts; thermal resistance 290 K/W vs. 220 K/W for SOT886 | Select when board assembly uses legacy SOT-23 tooling and space constraints are relaxed |
Compared with 74LVC1G57GW,125 and SN74AUP1G57DBVR, the 74AUP1G0832GM,115 delivers lowest static power, smallest footprint, and guaranteed IOFF behavior - making it optimal for space- and energy-critical embedded systems requiring deterministic power-down isolation.
Availability
74AUP1G0832GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power sequencing, IoT edge node wake-up logic, and automotive body control modules requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1G0832GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications requiring sub-microamp quiescent current, wide-VCC operation, and robust ESD tolerance - optimized for signal integrity in next-generation portable and embedded systems.
FAQ
What is the exact Boolean function implemented by the 74AUP1G0832GM,115?
The device implements Y = (A × B) + C - a fixed 3-input AND-OR structure where inputs A and B feed an AND gate whose output is OR'd with input C. This is confirmed in Table 4 (function table) and Figure 5 of the official Nexperia datasheet Rev. 7. No configuration pins or mode selection exist; the logic is hardwired.
Does the 74AUP1G0832GM,115 support true bidirectional IOFF operation?
No - IOFF disables only the output driver when VCC = 0 V, preventing backflow current from other powered rails into the device. Inputs remain high-impedance but do not actively clamp or isolate; the specification confirms VI and VO tolerate 0 V to 3.6 V during power-down, with ±0.75 μA leakage per terminal.
Can the 74AUP1G0832GM,115 operate reliably at 0.8 V supply with full speed performance?
Yes - propagation delay is characterized down to 0.8 V: 19.5 ns (typ) at CL = 5 pF, per Table 9. Input thresholds scale with VCC (VIH = 0.70 × VCC min), and output drive capability is maintained. However, VOH drops to VCC − 0.11 V and VOL rises to 0.11 V, requiring compatible receiver thresholds.
Is the XSON6 (SOT886) package of the 74AUP1G0832GM,115 leadless and RoHS-compliant?
Yes - the SOT886 package is leadless with six copper terminals, fully compliant with RoHS Directive 2011/65/EU and REACH SVHC regulations. The body is 1.0 mm × 1.45 mm × 0.5 mm, and terminal plating uses matte tin over nickel, per Nexperia's package drawing sot886_po (Issue date 04-07-22).
74AUP1G0832GM,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- AND/OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (1.45x1)
74AUP1G0832GM,115 FAQ
1.How can I place an order for 74AUP1G0832GM,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G0832GM,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G0832GM,115 reliable?
The price and inventory of 74AUP1G0832GM,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G0832GM,115 is usually 5 days.
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Once your 74AUP1G0832GM,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G0832GM,115?
For technical support, including 74AUP1G0832GM,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G0832GM,115 requirements.
6.How does Aetrix verify that 74AUP1G0832GM,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G0832GM,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G0832GM,115 meets industry standards.
7.What is the process for return or replacement of 74AUP1G0832GM,115?
All 74AUP1G0832GM,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G0832GM,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G0832GM,115 part is unused and in its original packaging.
Return procedure for 74AUP1G0832GM,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G0832GM,115 Tags
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