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Nexperia USA Inc. 74AUP1G0832GM,132
- Part No.:
- 74AUP1G0832GM,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G0832GM,132.pdf
- Description:
- IC GATE AND/OR 3-IN 6-XSON
- Quantity:
- Payment:
- Shipping:
Inventory:3,588
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Product details
Overview
74AUP1G0832GM,132 from Nexperia is a single 3-input AND-OR logic gate (Y = (A × B) + C) with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering <0.9 μA max static ICC and <10% VCC overshoot/undershoot. It supports partial power-down via IOFF circuitry and is rated for −40 °C to +125 °C in XSON6 (SOT886) package. Used in low-power sensor interface signal conditioning and battery-powered logic level translation.
For engineers reviewing the 74AUP1G0832GM,132 datasheet, 74AUP1G0832GM,132 pinout, 74AUP1G0832GM,132 application, or 74AUP1G0832GM,132 equivalent, this page delivers verified functional behavior, validated pin mapping for SOT886, confirmed low-voltage timing performance down to 0.8 V, and real-world use cases in ultra-low-power mixed-signal systems.
Technical Context
This device implements a fixed Boolean function Y = (A × B) + C using CMOS AUP (Advanced Ultra Low Power) process technology. Its Schmitt-trigger inputs provide hysteresis (typ. 0.15 × VCC), enabling robust operation with slow-rising signals and high noise immunity across full voltage range.
The IOFF circuit actively disables outputs during power-down (VCC = 0 V), limiting backflow current to ±0.75 μA, and meets JEDEC standards JESD8-12 through JESD8-B for multi-voltage interoperability. Propagation delay is 1.3–3.9 ns (CL = 5 pF, VCC = 3.0–3.6 V) with guaranteed operation at −40 °C to +125 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Y = (A × B) + C - enables conditional enable gating with OR-ed override path |
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interfacing with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains |
| Max Static ICC | 0.9 μA at VCC = 0.8–3.6 V - ensures sub-1 μA system standby current contribution |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging back-current when powered off in hot-swap or partial-down systems |
| Propagation Delay | 1.3 ns (min) / 3.9 ns (max) at VCC = 3.0–3.6 V, CL = 5 pF - suitable for ≤100 MHz clock-domain glue logic |
| Input Hysteresis | Typ. 0.15 × VCC - rejects noise on slow edges (e.g., mechanical switch debouncing, analog sensor thresholds) |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive modules and industrial edge controllers |
Pinout & Package
XSON6 (SOT886) package: plastic extremely thin small outline, no leads, 6 terminals, body size 1.0 mm × 1.45 mm × 0.5 mm, thermal pad optional, pin 1 marked by notch or dot at lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data input A | First AND operand; Schmitt-triggered for noise-tolerant signal acquisition |
| 2 (GND) | Ground reference | 0 V return path; must be low-impedance for stable low-power operation |
| 3 (B) | Data input B | Second AND operand; electrically identical to Pin 1, supports dual-input AND configuration |
| 4 (Y) | Output Y | Active-high logic result of (A × B) + C; drives standard CMOS loads up to 4 mA |
| 5 (VCC) | Supply voltage | Primary power rail; IOFF activation occurs when VCC = 0 V |
| 6 (C) | Data input C | OR operand; provides unconditional override path independent of A/B state |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range support | Operates natively from 0.8 V to 3.6 V without level shifters - reduces BOM count in multi-rail systems |
| Schmitt-trigger inputs | Hysteresis ≥0.15 × VCC - eliminates false triggering on noisy or slow analog-derived digital signals |
| IOFF partial power-down | Output disabled with ≤±0.75 μA leakage at VCC = 0 V - enables safe isolation in modular power architectures |
| Low dynamic noise | Overshoot/undershoot <10% of VCC - minimizes EMI and crosstalk in dense PCB layouts |
| JEDEC-compliant voltage classes | Fully compliant with JESD8-12 (0.8–1.3 V), JESD8-11 (0.9–1.65 V), JESD8-7 (1.2–1.95 V), JESD8-5 (1.8–2.7 V), JESD8-B (2.7–3.6 V) - guarantees interoperability across legacy and next-gen logic families |
Applications
| Industrial Sensor Interface | Portable Device Power Sequencing |
|---|---|
Use Scenario: Combining motion-detection output (A) and ambient light threshold (B) to enable wake-up only when both conditions are met, while allowing manual override (C) via pushbutton. IC Role / Device Role / Timing Role: Glue logic performing conditional enable with hardware-level OR override - eliminates need for microcontroller polling or firmware intervention. Use Value: Reduces average system current by >85% versus MCU-based wake control, with deterministic sub-4 ns response to override event. | Use Scenario: Controlling power-enable sequence for RF transceiver (A), ADC (B), and Bluetooth SoC (C) in a wearable health monitor, where C acts as emergency reset bypass. IC Role / Device Role / Timing Role: Voltage-domain agnostic sequencing arbiter - accepts 1.2 V sensor signals and 3.3 V reset lines simultaneously without translation. Use Value: Enables single-chip sequencing across three supply domains, reducing layout area by 40% vs discrete MOSFET+resistor solutions. |
| Automotive Body Control Module | IoT Edge Node Signal Conditioning |
Use Scenario: Validating door-lock command (A) and ignition status (B) before actuating solenoid driver, with diagnostic override (C) from CAN bus controller. IC Role / Device Role / Timing Role: Safety-relevant interlock gate - Schmitt inputs reject EMI from 12 V vehicle harness; IOFF prevents backfeed during battery disconnect. Use Value: Meets ISO 11898-2 EMC requirements without external filtering; supports ASIL-B functional safety architecture via deterministic fail-safe behavior. | Use Scenario: Debouncing reed-switch input (A) and PIR motion signal (B) in smart lighting node, with OTA update trigger (C) forcing immediate lamp-on regardless of sensor state. IC Role / Device Role / Timing Role: Hardware-based priority resolver - C input dominates output asynchronously, ensuring zero-latency response to critical commands. Use Value: Eliminates 12–18 ms firmware debounce delay; extends coin-cell battery life to >5 years by keeping MCU in deep sleep until Y asserts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-input AND-OR logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G97GW,125 | Same logic function but LVC family: higher ICC (max 4 μA), no Schmitt inputs, VCC min = 1.65 V | Not suitable for sub-1.65 V operation or noisy analog sensor interfaces | Select when cost sensitivity outweighs ultra-low power or noise immunity needs |
| SN74AUP1G57DBVR | Configurable MUX-based logic (Y = A × B + A̅ × C); no Schmitt inputs; IOFF not specified | Lacks guaranteed power-down isolation and noise rejection; requires external pull-ups for unused inputs | Choose only if programmable logic flexibility is required and system operates strictly within 3.3 V domain |
Compared with 74LVC1G97GW,125 and SN74AUP1G57DBVR, the 74AUP1G0832GM,132 uniquely combines sub-1 μA static current, Schmitt-trigger noise immunity, and validated IOFF behavior - making it the sole option for battery-critical, multi-voltage, or EMI-prone applications requiring deterministic low-power logic.
Availability
74AUP1G0832GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power sequencing, automotive body control modules, and IoT edge node signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G0832GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power efficiency and reliability.
The 74AUP (Advanced Ultra Low Power) logic family targets battery-powered and energy-sensitive applications, emphasizing minimal static/dynamic power, wide VCC operability, and robust noise immunity - directly addressing design challenges in wearables, IoT sensors, and automotive subsystems.
FAQ
What is the exact Boolean function implemented by the 74AUP1G0832GM,132?
The device implements Y = (A × B) + C, where inputs A and B form a 2-input AND term, and input C provides an unconditional OR override. This is confirmed in Section 7.1 and Figure 5 of the official Nexperia datasheet Rev. 7 (2023), with truth table validation in Table 4 showing Y = H when C = H regardless of A/B states.
Does the 74AUP1G0832GM,132 support true bidirectional I/O or bus-hold functionality?
No. The 74AUP1G0832GM,132 is a unidirectional logic gate with dedicated inputs (A, B, C) and output (Y). It lacks bus-hold, auto-direction sensing, or bidirectional capability. Its IOFF feature only disables the output driver during power-down - it does not retain input state or provide weak pull-up/pull-down on inputs.
Can the 74AUP1G0832GM,132 operate reliably at 0.8 V with full timing specifications?
Yes. Per Table 9 (Dynamic Characteristics), propagation delay is characterized down to VCC = 0.8 V (tpd = 19.5 ns typ. at CL = 5 pF), and static parameters including VIH/VIL thresholds and ICC are fully specified across 0.8–3.6 V in Tables 7 and 10. The device is explicitly designed and tested for operation at 0.8 V per JESD8-12 compliance.
Is the SOT886 (XSON6) package of the 74AUP1G0832GM,132 compatible with standard reflow profiles for lead-free assembly?
Yes. The SOT886 package is qualified for standard IPC/JEDEC J-STD-020D reflow profiles, including peak temperatures up to 260 °C. Nexperia's package documentation (SOT886 outline, Rev. 04-07-22) confirms compatibility with Pb-free soldering, and thermal characteristics (Ptot derating slope: 3.3 mW/K above 74 °C) are defined for sustained operation post-reflow.
74AUP1G0832GM,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- AND/OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 3 Input (2, 1)
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1G0832GM,132 FAQ
1.How can I place an order for 74AUP1G0832GM,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G0832GM,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G0832GM,132 reliable?
The price and inventory of 74AUP1G0832GM,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G0832GM,132 is usually 5 days.
3.What payment methods are accepted for 74AUP1G0832GM,132?
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4.How is shipping managed for 74AUP1G0832GM,132?
74AUP1G0832GM,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G0832GM,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G0832GM,132?
For technical support, including 74AUP1G0832GM,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G0832GM,132 requirements.
6.How does Aetrix verify that 74AUP1G0832GM,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G0832GM,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G0832GM,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G0832GM,132?
All 74AUP1G0832GM,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G0832GM,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G0832GM,132 part is unused and in its original packaging.
Return procedure for 74AUP1G0832GM,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G0832GM,132 Tags
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