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Nexperia USA Inc. 74AUP1G0832GS,132
- Part No.:
- 74AUP1G0832GS,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G0832GS,132.pdf
- Description:
- IC GATE AND/OR 3-IN 6X2SON
- Quantity:
- Payment:
- Shipping:
Inventory:2,673
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Product details
Overview
74AUP1G0832GS,132 from Nexperia is a single 3-input AND-OR logic gate (Y = (A × B) + C) with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering <0.9 μA max static ICC, <10% VCC overshoot/undershoot, and IOFF-enabled partial power-down protection. It serves in low-power sensor interface signal conditioning and battery-powered control logic where input noise immunity and rail-to-rail compatibility are critical.
For engineers reviewing the 74AUP1G0832GS,132 datasheet, 74AUP1G0832GS,132 pinout, 74AUP1G0832GS,132 application, or 74AUP1G0832GS,132 equivalent, this device supports voltage-scalable digital interfacing in space-constrained industrial and portable systems requiring sub-1 μA quiescent current and guaranteed operation down to 0.8 V.
Technical Context
This device implements a fixed Boolean function Y = (A × B) + C using CMOS logic with Schmitt-trigger inputs-ensuring robust switching despite slow or noisy input edges. Its IOFF circuit actively disables outputs during VCC = 0 V, blocking backflow current in partial power-down modes.
It complies with JEDEC standards JESD8-12 through JESD8-B across five VCC ranges and meets HBM ESD >5000 V and CDM >1000 V. The logic is fully specified from –40 °C to +125 °C in the SOT1202 XSON6 package (1.0 × 1.0 × 0.35 mm).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Y = (A × B) + C - enables compact implementation of combined AND/OR decision logic without external gates |
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interfacing with 0.8 V I/O domains (e.g., advanced MCUs) and legacy 3.3 V systems |
| Max Static ICC | 0.9 μA at VCC = 0.8–3.6 V - ensures ultra-low standby power in always-on monitoring circuits |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging back-current when powered off while inputs remain active |
| Propagation Delay | 1.2 ns (min) to 3.9 ns (max) at VCC = 3.0–3.6 V, CL = 5 pF - delivers timing predictability for high-speed enable/control paths |
| Input Thresholds | VIL ≤ 0.30×VCC, VIH ≥ 0.70×VCC (at VCC = 0.8 V) - provides wide noise margin and stable switching under varying VCC |
| ESD Rating | HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in board-level I/O zones |
Pinout & Package
XSON6 package (SOT1202): plastic extremely thin small outline, no leads, 6 terminals, body size 1.0 × 1.0 × 0.35 mm, thermal pad optional, pin 1 marked by lower-left corner notch below marking code "aY".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data input A | First AND operand; Schmitt-triggered for noise rejection on slow-rising signals |
| 2 (GND) | Ground reference | 0 V return path; must be low-impedance to maintain noise immunity and output drive integrity |
| 3 (B) | Data input B | Second AND operand; electrically identical to Pin 1, enabling symmetric layout routing |
| 4 (Y) | Data output Y | Active-high result of (A × B) + C; drives standard CMOS loads up to ±4 mA at 3.0 V |
| 5 (VCC) | Supply voltage | Primary power rail; powers internal logic and output stage; decoupling capacitor required within 2 mm |
| 6 (C) | Data input C | OR operand; bypasses AND stage - allows direct assertion of output independent of A/B state |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable switching with input rise/fall times up to 200 ns/V - eliminates external hysteresis components |
| IOFF partial power-down | Outputs float safely when VCC = 0 V, preventing backfeed into powered subsystems - critical for hot-swap and multi-rail designs |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC level - allows interfacing with higher-voltage peripherals without level shifters |
| Low dynamic noise | Overshoot/undershoot limited to <10% of VCC - reduces EMI and avoids false triggering in adjacent signal lines |
| Wide temperature range | Specified from –40 °C to +125 °C - supports deployment in automotive under-hood, industrial PLC, and outdoor IoT nodes |
Applications
| Industrial Sensor Hub | Portable Device Power Sequencing |
|---|---|
Use Scenario: Aggregating fault signals from multiple analog sensors (temperature, pressure, humidity) before forwarding to MCU interrupt line. IC Role / Device Role / Timing Role: Logic combiner implementing OR-of-AND condition: trigger if (sensor_A_OK AND sensor_B_OK) OR sensor_C_FAULT. Use Value: Reduces PCB footprint vs discrete gate solution; Schmitt inputs reject noise from long sensor traces; IOFF prevents leakage when MCU sleeps. |
Use Scenario: Enabling system power rails only after all preconditions (battery OK, thermal safe, firmware validated) are met. IC Role / Device Role / Timing Role: Final gating element in power-enable chain: Y = (BAT_OK × THERM_OK) + FW_VALID - asserts EN when either safety check passes or firmware confirms readiness. Use Value: Eliminates need for microcontroller GPIO polling; operates at 0.8 V to coordinate with ultra-low-VDD subsystems; sub-μA ICC extends battery life. |
| USB-C Port Controller Interface | IoT Edge Node Wake-Up Arbiter |
Use Scenario: Interfacing USB-C CC logic outputs to a host controller's wake-up input, combining orientation detection and accessory presence. IC Role / Device Role / Timing Role: Signal conditioner translating dual CC line states into single wake event: Y = (CC1_DETECTED × CC2_DETECTED) + ACCESSORY_ATTACHED. Use Value: Overvoltage-tolerant inputs accept 3.3 V CC logic even when VCC = 1.2 V; fast propagation (<4 ns) ensures timely wake response. |
Use Scenario: Prioritizing wake sources (motion sensor, BLE packet, button press) in a battery-operated environmental monitor. IC Role / Device Role / Timing Role: Priority resolver: Y = (MOTION_ACTIVE × BLE_READY) + BUTTON_PRESSED - asserts wake only when BLE stack is ready *or* manual override occurs. Use Value: Schmitt inputs suppress contact bounce on mechanical button; 0.9 μA ICC preserves multi-year battery life; operates reliably at 1.1 V during brownout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-input AND-OR logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G97DBVR | Same Y = (A × B) + C function but no Schmitt inputs; VCC = 1.65–5.5 V; higher ICC (max 10 μA) | Lacks noise immunity on slow inputs; requires external filtering in noisy environments | Select when interfacing clean, fast-switching signals and wider VCC range (up to 5.5 V) is needed |
| 74AUP1G57GW,125 | Configurable MUX-based gate (Y = A × (B + C)); same VCC range, IOFF, and Schmitt inputs; different logic equation | Cannot replicate exact (A × B) + C behavior without reworking logic flow | Choose only if design can adapt to A × (B + C) - offers flexibility but not functional equivalence |
Compared with SN74LVC1G97DBVR and 74AUP1G57GW,125, the 74AUP1G0832GS,132 uniquely combines Schmitt-triggered inputs, sub-1 μA ICC, and the precise (A × B) + C function in a 1.0 mm² XSON6 package - making it optimal for noise-prone, ultra-low-power embedded control where logic topology and quiescent current are non-negotiable.
Availability
74AUP1G0832GS,132 is available at Aetrix Electronics and suitable for industrial sensor hubs, portable device power sequencing, USB-C interface conditioning, and IoT edge node wake-up arbitration requiring stable component supply across extended temperature and ultra-low-power constraints.
Supply support for 74AUP1G0832GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications demanding sub-microamp quiescent current, wide VCC scalability, and robust noise immunity - exemplified by the 74AUP1G0832GS,132's 0.8 V–3.6 V operation and Schmitt-trigger inputs.
FAQ
Does the 74AUP1G0832GS,132 support true bidirectional I/O or bus-hold functionality?
No. It is a unidirectional logic gate with dedicated input (Pins 1, 3, 6), output (Pin 4), supply (Pin 5), and ground (Pin 2) terminals. It lacks bus-hold circuitry, auto-direction sensing, or I²C-compatible open-drain capability. Its IOFF feature only disables the output driver during power-down - it does not provide passive pull-up/down or data retention.
Can Pin 6 (C) be used as an asynchronous set input to force Y = HIGH regardless of A and B states?
Yes. Per the function table and Fig. 5, when C = HIGH, Y = HIGH irrespective of A and B values - effectively acting as an asynchronous enable or override input. This behavior is inherent to the Y = (A × B) + C Boolean equation and is fully characterized across –40 °C to +125 °C and 0.8 V–3.6 V VCC.
What is the maximum capacitive load the 74AUP1G0832GS,132 can drive while maintaining specified tpd and VOH/VOL?
The device is characterized up to CL = 30 pF (Table 9), with tpd increasing from 1.2 ns to 7.0 ns and VOL rising from 0.36 V to 0.50 V at VCC = 3.0 V. Driving >30 pF risks violating timing specs and output voltage margins; for heavier loads, add a buffer stage or reduce trace capacitance via layout optimization.
Is the SOT1202 (XSON6) package of the 74AUP1G0832GS,132 compatible with standard reflow profiles for lead-free assembly?
Yes. The SOT1202 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1) and supports standard Pb-free reflow profiles with peak temperatures up to 260 °C. Its 0.35 mm height and 1.0 mm pitch allow compatibility with fine-pitch stencil printing and automated optical inspection.
74AUP1G0832GS,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- AND/OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 3 Input (2, 1)
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT1202 (1x1)
74AUP1G0832GS,132 FAQ
1.How can I place an order for 74AUP1G0832GS,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G0832GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G0832GS,132 reliable?
The price and inventory of 74AUP1G0832GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G0832GS,132 is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G0832GS,132 transactions.
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4.How is shipping managed for 74AUP1G0832GS,132?
74AUP1G0832GS,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G0832GS,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G0832GS,132?
For technical support, including 74AUP1G0832GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G0832GS,132 requirements.
6.How does Aetrix verify that 74AUP1G0832GS,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G0832GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G0832GS,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G0832GS,132?
All 74AUP1G0832GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G0832GS,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G0832GS,132 part is unused and in its original packaging.
Return procedure for 74AUP1G0832GS,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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