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Nexperia USA Inc. 74AUP1G0832GW,125
- Part No.:
- 74AUP1G0832GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
74AUP1G0832GW,125.pdf
- Description:
- IC GATE AND/OR 3-IN 6TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,419
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Product details
Overview
74AUP1G0832GW,125 from Nexperia is a single 3-input AND-OR logic gate (Y = (A × B) + C) with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ≤0.9 μA max static ICC, IOFF-enabled partial power-down protection, and −40 °C to +125 °C temperature rating in TSSOP6 (SOT363-2) package. It serves as a low-power combinational logic element in battery-powered sensor interfaces and voltage-level-flexible control signal conditioning.
For engineers reviewing the 74AUP1G0832GW,125 datasheet, 74AUP1G0832GW,125 pinout, 74AUP1G0832GW,125 application, or 74AUP1G0832GW,125 equivalent, this device supports ultra-low-voltage logic interfacing, noise-immune input handling, and safe I/O isolation during system power sequencing - critical for portable instrumentation, industrial PLC I/O modules, and multi-rail MCU peripheral coordination.
Technical Context
This device implements a fixed Boolean function Y = (A × B) + C using CMOS AUP (Advanced Ultra-low Power) process technology. Its Schmitt-trigger inputs provide hysteresis (typ. 0.15 × VCC), enabling robust operation with slow-rising signals and high noise immunity (>70% of VCC).
The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, and all inputs tolerate up to 3.6 V regardless of VCC level - supporting mixed-voltage domain interfacing without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | 3-input AND-OR: Y = (A × B) + C - enables compact implementation of conditional enable logic without discrete gates |
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max Static ICC | 0.9 μA at VCC = 3.6 V - ensures negligible quiescent drain in always-on monitoring circuits |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging back-current during hot-swap or partial power-down sequences |
| Propagation Delay | 1.2 ns (min) to 3.9 ns (max) at VCC = 3.3 V, CL = 5 pF - meets timing requirements for sub-200 MHz control-path logic |
| Input Hysteresis | Typ. 0.15 × VCC - rejects <10 ns noise spikes and accommodates RC-filtered or long-trace inputs |
| ESD Rating | HBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without shielding |
Pinout & Package
TSSOP6 (SOT363-2) plastic thin shrink small outline package: 6-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data input A | First AND operand; Schmitt-triggered for noise margin and slow-edge tolerance |
| 2 (GND) | Ground reference | 0 V return path for logic and power; must be low-impedance for stable noise immunity |
| 3 (B) | Data input B | Second AND operand; electrically identical to Pin 1, supports independent signal routing |
| 4 (Y) | Data output Y | Active-high result of (A × B) + C; drives standard CMOS loads up to 4 mA sink/source |
| 5 (VCC) | Supply voltage | Primary power rail; powers internal logic and enables IOFF control when de-asserted |
| 6 (C) | Data input C | OR operand; bypasses AND stage - enables direct assertion of output independent of A/B state |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (0.8–3.6 V) | Eliminates need for separate level translators when interfacing 1.2 V FPGA I/O with 3.3 V microcontroller peripherals |
| Schmitt-trigger inputs | Enables reliable operation with RC-debounced switches or attenuated sensor outputs without added hysteresis circuitry |
| IOFF partial power-down | Allows safe insertion/removal of logic in live backplanes or modular subsystems without disrupting adjacent powered rails |
| Overvoltage-tolerant inputs | Accepts 0–3.6 V signals even at VCC = 0.8 V - simplifies interconnection with higher-voltage legacy sensors or DACs |
| Low dynamic noise | Overshoot/undershoot <10% of VCC - reduces crosstalk risk in dense PCB layouts with shared ground planes |
Applications
| Industrial Sensor Interface | Portable Medical Device Logic |
|---|---|
|
Use Scenario: Combining motion-detection interrupt (A), low-battery flag (B), and manual override button (C) to drive a single LED alert output (Y). IC Role / Device Role / Timing Role: Combinational logic arbiter performing real-time priority resolution without MCU intervention. Use Value: Reduces active power by eliminating polling loops; Schmitt inputs reject EMI from motor drivers near the sensor node. |
Use Scenario: Enabling a low-power ADC sampling trigger only when both sleep-mode exit condition (A) and valid calibration status (B) are met, with emergency abort (C) overriding all. IC Role / Device Role / Timing Role: Asynchronous control gate ensuring deterministic wake-up response within 4 ns at 1.8 V. Use Value: Guarantees sub-microsecond reaction to life-critical events while maintaining <1 μA standby draw. |
| Automated Test Equipment (ATE) Signal Routing | IoT Edge Node Power Sequencing |
|
Use Scenario: Gating test pattern clock delivery to DUT based on pass/fail status (A), test mode select (B), and hardware lockout (C). IC Role / Device Role / Timing Role: High-reliability signal combiner in 100+ channel parallel test systems. Use Value: IOFF prevents backfeed into disabled test channels during reconfiguration, avoiding false triggers. |
Use Scenario: Coordinating activation of BLE radio (Y) only after PMIC confirms stable 3.3 V (A), LDO reports clean 1.2 V (B), and firmware releases hold (C). IC Role / Device Role / Timing Role: Hardware-enforced power-up dependency checker independent of software state. Use Value: Eliminates race conditions during cold start; operates correctly across full −40 °C to +125 °C ambient range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-input AND-OR logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G97GW,125 | Higher ICC (max 4 μA), no Schmitt inputs, same TSSOP6 package | Lacks noise immunity for unfiltered inputs; requires external RC or hysteresis for slow edges | Select when cost sensitivity outweighs noise margin needs and inputs are already conditioned |
| SN74AUP1G57DBVR | Configurable MUX-based logic (Y = A × B + A̅ × C); different pinout; SOT-23-6 package | Supports alternate functions (XOR, inverter) but requires re-layout; no IOFF support | Choose only if programmable logic flexibility is required and board redesign is acceptable |
Compared with 74LVC1G97GW,125 and SN74AUP1G57DBVR, the 74AUP1G0832GW,125 uniquely combines guaranteed Schmitt-trigger noise rejection, ultra-low static current, and IOFF safety in a fixed-function AND-OR topology - making it optimal for space-constrained, battery-sensitive, and mixed-voltage control applications where reliability trumps configurability.
Availability
74AUP1G0832GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automated test equipment, and IoT edge node power sequencing requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AUP1G0832GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, with leadership in logic, discrete, and MOSFET technologies serving automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) logic family targets energy-constrained applications demanding sub-1 μA static current, wide VCC scalability, and robust signal integrity - designed specifically for battery-powered and thermally restricted embedded systems.
FAQ
Does 74AUP1G0832GW,125 support true 0.8 V operation with full logic swing?
Yes. At VCC = 0.8 V, VIH is guaranteed ≥0.70 × VCC (≥0.56 V) and VOL ≤0.1 V with 20 μA load, enabling interoperability with other 0.8 V logic families. Propagation delay remains specified at 19.5 ns (typ) for CL = 5 pF.
Can Pin 6 (C) be used as an asynchronous set input independent of A and B states?
Yes. The Boolean function Y = (A × B) + C means C acts as a direct OR term: asserting C = HIGH forces Y = HIGH regardless of A and B values. This enables priority override functionality without modifying upstream signals.
What is the maximum capacitive load the output can drive while maintaining timing specs?
The device is characterized up to CL = 30 pF. At VCC = 3.3 V, tpd increases from 3.2 ns (CL = 5 pF) to 5.9 ns (CL = 30 pF). For designs requiring <4 ns delay, keep total load ≤15 pF including trace and input capacitance of downstream devices.
Is the TSSOP6 package (SOT363-2) RoHS-compliant and lead-free?
Yes. Per Nexperia's product compliance documentation, SOT363-2 packaging for 74AUP1G0832GW,125 is lead-free, RoHS-compliant, and halogen-free, with terminal finish NiPdAu and moisture sensitivity level (MSL) 1 at floor life unlimited when stored ≤30 °C/60% RH.
74AUP1G0832GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- AND/OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 3 Input (2, 1)
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
74AUP1G0832GW,125 FAQ
1.How can I place an order for 74AUP1G0832GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G0832GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G0832GW,125 reliable?
The price and inventory of 74AUP1G0832GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G0832GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G0832GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G0832GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G0832GW,125?
74AUP1G0832GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G0832GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G0832GW,125?
For technical support, including 74AUP1G0832GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G0832GW,125 requirements.
6.How does Aetrix verify that 74AUP1G0832GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G0832GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G0832GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G0832GW,125?
All 74AUP1G0832GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G0832GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G0832GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G0832GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G0832GW,125 Tags
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