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Nexperia USA Inc. 74AUP1G08GW,125
- Part No.:
- 74AUP1G08GW,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G08GW,125.pdf
- Description:
- IC GATE AND 1CH 2-INP 5TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:10,890
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Product details
Overview
74AUP1G08GW,125 from Nexperia is a single 2-input CMOS AND gate in TSSOP5 (SOT353-1) package, operating from 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF circuitry for partial power-down protection, and guarantees ≤0.9 μA max ICC across -40 °C to +125 °C. Used in low-power logic interfacing, voltage-level translation, and battery-powered sensor signal conditioning.
For engineers reviewing the 74AUP1G08GW,125 datasheet, 74AUP1G08GW,125 pinout, 74AUP1G08GW,125 application, or 74AUP1G08GW,125 equivalent, this page delivers verified functional behavior, validated pin mapping for TSSOP5, confirmed static/dynamic specs at 0.8–3.6 V, and real-world use cases in ultra-low-power embedded control and I/O expansion circuits.
Technical Context
This device implements standard positive-logic AND functionality with Schmitt-trigger input thresholds-VIH ≥0.65×VCC and VIL ≤0.35×VCC over 0.9–1.95 V VCC range-enabling robust operation with slow-rising signals. Its IOFF circuit actively disables outputs during power-down, limiting backflow current to ±0.75 μA when VCC = 0 V.
Propagation delay ranges from 0.9 ns (VCC = 3.6 V, CL = 5 pF) to 24.1 ns (VCC = 0.8 V, CL = 15 pF), with CPD = 4.0 pF at 3.3 V enabling precise dynamic power estimation. Input capacitance is 0.8 pF and output capacitance is 1.7 pF, supporting high-speed signal integrity in compact PCB layouts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (Static) | 0.9 μA at -40 °C to +125 °C - enables multi-year battery life in always-on IoT endpoint nodes. |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging back-current when one rail is powered down in mixed-supply systems. |
| tpd (Typical) | 2.2 ns at VCC = 3.3 V, CL = 5 pF - sufficient for 100+ MHz clock-domain gating in microcontroller peripherals. |
| Input Thresholds | VIH ≥0.65×VCC, VIL ≤0.35×VCC (1.1–1.95 V VCC) - ensures reliable switching with noisy or slew-limited GPIO signals. |
| ESD Rating | HBM >5000 V, CDM >1000 V - meets industrial-grade robustness requirements without external protection. |
| Operating Temp | -40 °C to +125 °C - qualified for under-hood automotive, industrial motor control, and outdoor edge devices. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, 0.3 mm max height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | B | Second logic input; Schmitt-triggered, tolerant of slow edges and noise up to 3.6 V regardless of VCC. |
| 2 | A | Primary logic input; identical electrical behavior to Pin 1; dual-input AND function requires both asserted HIGH. |
| 3 | GND | Ground reference (0 V); must be connected directly to system ground plane to maintain noise immunity and IOFF integrity. |
| 4 | Y | Open-drain compatible output; drives HIGH/LOW per AND truth table; supports 4 mA sink at VCC = 3.0 V. |
| 5 | VCC | Power supply input; decoupling capacitor (100 nF) required within 3 mm for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables clean logic transitions with input rise/fall times up to 200 ns/V - eliminates need for external RC filtering. |
| IOFF partial power-down | Disables output and limits leakage to ±0.75 μA when VCC = 0 V - critical for hot-swap and multi-rail power sequencing. |
| Overvoltage-tolerant inputs | Accepts 0–3.6 V signals independent of VCC setting - allows safe interfacing with higher-voltage peripherals. |
| Ultra-low dynamic power | CPD = 4.0 pF at 3.3 V enables <1 μW dynamic dissipation at 1 MHz - ideal for duty-cycled sensor wake-up logic. |
| Wide temperature qualification | Specified from -40 °C to +125 °C - supports deployment in engine control units, industrial PLCs, and solar inverters. |
Applications
| Industrial Sensor Interface | Low-Power Microcontroller I/O Expansion |
|---|---|
|
Use Scenario: Signal conditioning for analog sensor outputs feeding into ADC channels of an ARM Cortex-M0+ MCU running at 1.8 V. IC Role / Device Role / Timing Role: AND gate acts as enable-controlled signal pass-through, synchronizing sensor data capture only when system is awake and VCC = 1.8 V. Use Value: Schmitt-trigger inputs reject EMI-induced glitches on long sensor traces; IOFF prevents backfeed when MCU enters deep sleep and VCC drops to 0 V. |
Use Scenario: Adding two extra GPIO-controlled functions (e.g., LED blink control and fault latch) to a space-constrained wearable device using a 3.3 V SoC. IC Role / Device Role / Timing Role: Configured as active-HIGH enable gate: one input tied to SoC GPIO, other to pushbutton; output drives LED driver or latch input. Use Value: 0.9 μA max ICC extends battery runtime by >2 years in standby; TSSOP5 footprint (1.25 mm × 2.2 mm) fits tight layout constraints. |
| Automotive Body Control Module | USB-C Power Delivery Sequencing |
|
Use Scenario: Interlocking door-lock actuator enable with ignition status and door-closed sensor in a 12 V vehicle platform using 3.3 V domain logic. IC Role / Device Role / Timing Role: Performs safety-critical AND of "ignition ON" and "door closed" signals before enabling lock motor driver. Use Value: -40 °C to +125 °C rating ensures reliability under hood; overvoltage-tolerant inputs accept 5 V sensor signals without level shifters. |
Use Scenario: Enabling VBUS discharge path only after USB-C CC line negotiation confirms sink role and VBUS is safe to disconnect. IC Role / Device Role / Timing Role: Gates discharge MOSFET control signal using CC detection and VBUS_OK status as dual inputs. Use Value: IOFF blocks reverse current flow when VBUS rail collapses first during unplug event; 2.2 ns tpd ensures sub-microsecond response to fault conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input AND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G08DBVR | Higher ICC (max 10 μA), no Schmitt inputs, VCC min = 1.65 V - lacks slow-edge tolerance and ultra-low standby current. | Not suitable for sub-1.65 V operation or battery-critical designs requiring <1 μA sleep current. | Select only if system operates strictly at 1.8 V+ and does not require noise-immune inputs. |
| 74LVC1G08GW,125 | Same TSSOP5 package but higher ICC (max 10 μA), no IOFF, narrower temp range (-40 °C to +85 °C). | Cannot support hot-swap or partial power-down architectures; unsuitable for under-hood or extended-temp deployments. | Choose only for cost-sensitive consumer applications where 125 °C rating and IOFF are unnecessary. |
Compared with SN74LVC1G08DBVR and 74LVC1G08GW,125, the 74AUP1G08GW,125 uniquely combines sub-1 μA ICC, Schmitt-trigger inputs, IOFF, and -40 °C to +125 °C operation - making it the sole option for ultra-low-power, high-reliability, mixed-rail embedded control.
Availability
74AUP1G08GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, low-power microcontroller I/O expansion, and USB-C power delivery sequencing requiring stable component supply across extended temperature and ultra-low-power profiles.
Supply support for 74AUP1G08GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components - including logic, discrete, and MOSFET devices - with leadership in high-volume manufacturing and automotive-grade reliability.
The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications, delivering nanowatt static power, wide VCC range, and robust IO architecture for next-generation portable and industrial electronics.
FAQ
Does 74AUP1G08GW,125 support true bidirectional signal routing?
No. The 74AUP1G08GW,125 is a unidirectional AND gate with defined inputs (A, B) and output (Y). It lacks bus-hold, direction control, or transmission-gate architecture. Its IOFF feature only disables output drive during power-down - it does not enable signal flow from Y to A/B. Bidirectional use requires dedicated transceivers or analog switches.
Can I operate 74AUP1G08GW,125 at 0.7 V supply to extend battery life further?
No. Absolute minimum VCC is 0.8 V per datasheet limiting values (Table 5). Operation below 0.8 V risks undefined logic states, increased propagation delay variability, and potential failure to meet VIH/VIL thresholds. For sub-0.8 V systems, consider energy-harvesting PMICs or voltage boosters prior to logic supply.
Is the TSSOP5 package (SOT353-1) compatible with standard reflow profiles for lead-free assembly?
Yes. SOT353-1 is qualified for JEDEC J-STD-020D-compliant lead-free reflow, with peak temperature up to 260 °C for ≤30 seconds. Its 0.65 mm pitch and gull-wing leads support automated optical inspection (AOI) and standard SPI-based solder paste deposition. Recommend 100 nF X7R ceramic decoupling placed adjacent to Pin 5 (VCC).
How does the Schmitt-trigger input improve performance in noisy automotive environments?
Schmitt-trigger inputs provide hysteresis (typically ~150 mV at 1.8 V), meaning VIH and VIL differ by a fixed voltage margin. This prevents multiple output toggles caused by slow-rising noise on sensor lines - e.g., in CAN/LIN stubs or alternator-ripple-affected analog rails - ensuring single, clean transitions even with 100+ ns edge jitter.
74AUP1G08GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- AND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.2ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G08GW,125 FAQ
1.How can I place an order for 74AUP1G08GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G08GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G08GW,125 reliable?
The price and inventory of 74AUP1G08GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G08GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G08GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G08GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G08GW,125?
74AUP1G08GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G08GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G08GW,125?
For technical support, including 74AUP1G08GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G08GW,125 requirements.
6.How does Aetrix verify that 74AUP1G08GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G08GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G08GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G08GW,125?
All 74AUP1G08GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G08GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G08GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G08GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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