Diodes Incorporated 74AUP1G09FS3-7

Overview

74AUP1G09FS3-7 from Diodes Incorporated is a single 2-input positive AND gate with open-drain output, designed for ultra-low-power logic interfacing in battery-operated systems. It operates across 0.8V–3.6V supply, delivers 4mA output drive at 3.0V, features IOFF partial power-down protection, and includes Schmitt-trigger inputs with ~250mV hysteresis at VCC = 3.0V-enabling robust signal conditioning in noisy portable electronics.

For engineers reviewing the 74AUP1G09FS3-7 datasheet, 74AUP1G09FS3-7 pinout, 74AUP1G09FS3-7 application, or 74AUP1G09FS3-7 equivalent, this device is selected for its sub-1µA static current, nanosecond-scale propagation delay (e.g., 2.3ns typ @ 3.3V/5pF), open-drain flexibility for wired-AND bus configurations, and validated operation down to -40°C in space-constrained DFN packaging.

Technical Context

This AUP-family gate implements Boolean Y = A • B with open-drain output, requiring an external pull-up for high-level assertion. Its IOFF circuit actively disables output leakage during partial power-down, preventing backflow when VCC = 0 while inputs remain biased.

Schmitt-trigger inputs provide noise immunity with voltage-dependent hysteresis (250mV typ at 3.0V), enabling reliable operation with slow-rising signals. The device supports dynamic switching up to 125°C ambient and exhibits low dynamic capacitance (Cpd = 6.1pF typ @ 3.3V), minimizing AC power dissipation in high-frequency enable/control paths.

Key Specifications

Pinout & Package

X2-DFN0808-4 package: 0.8mm × 0.8mm × 0.35mm body, diamond pad layout, 0.5mm pad pitch, no leads, bottom thermal pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input AND gate applications.

Compared with SN74LVC1G09DBVR and 74AUP1G08FS3-7, the 74AUP1G09FS3-7 uniquely combines ultra-low ICC, IOFF, Schmitt inputs, and open-drain output in a 0.8mm × 0.8mm footprint-making it irreplaceable for battery-sensitive, multi-rail, and bus-shared control logic.

Availability

74AUP1G09FS3-7 is available at Aetrix Electronics and suitable for smartphone power sequencing, IoT sensor node wake-up, wearable health monitor reset logic, and industrial PLC input conditioning requiring stable component supply across extended temperature and low-power design constraints.

Supply support for 74AUP1G09FS3-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability, low-power, and miniaturized solutions for consumer, industrial, and computing markets.

The 74AUP logic family targets ultra-low-power portable electronics, delivering sub-microwatt static operation and wide-VCC compatibility to extend battery life without sacrificing speed or noise immunity.

FAQ

Can 74AUP1G09FS3-7 operate with a 0.9V supply?

Yes. The device is fully specified from 0.8V to 3.6V, including propagation delay (13.5ns max @ 0.8V/5pF), input thresholds (VIH = 0.8×VCC), and output drive (20µA min @ 0.8V). This makes it suitable for energy-harvesting systems and near-threshold logic designs where supply rails dip below 1.0V.

What is the maximum capacitive load the open-drain output can drive?

The output is characterized up to 30pF load capacitance, with tpd increasing from 2.3ns (5pF) to 12.7ns (30pF) at 3.3V. For reliable rise time, use a pull-up resistor ≤10kΩ with CL ≤15pF; heavier loads require larger pull-ups or buffer stages to maintain timing margins.

Does the X2-DFN0808-4 package have a thermal pad?

No. The X2-DFN0808-4 package has four perimeter pads only (A, Y, GND, B); there is no exposed thermal pad. Thermal resistance is θJA = 430°C/W, so power dissipation must remain below ~15mW in still-air environments to avoid exceeding 125°C junction temperature.

How does IOFF behave when VCC = 0V but inputs are pulled to 3.3V?

IOFF actively disables the output FET, limiting leakage to ±0.5µA max over temperature. This prevents reverse current from the 3.3V input rail into the unpowered VCC node-critical for hot-plug safety and avoiding unintended power domain coupling in modular systems.