Diodes Incorporated 74AUP1G09FW5-7

Overview

74AUP1G09FW5-7 from Diodes Incorporated is a single 2-input positive AND gate with open-drain output, designed for ultra-low-power portable systems operating from 0.8V to 3.6V. It features IOFF partial power-down protection, Schmitt-trigger inputs (250 mV hysteresis at 3.0V), and delivers 4 mA output drive at 3.0V. Used in battery-powered mobile interfaces where level-shifting and wired-OR logic are required.

For engineers reviewing the 74AUP1G09FW5-7 datasheet, 74AUP1G09FW5-7 pinout, 74AUP1G09FW5-7 application, or 74AUP1G09FW5-7 equivalent, key selection criteria include supply voltage range (0.8–3.6 V), open-drain output compatibility with I²C and SMBus, IOFF-enabled power sequencing, and sub-1 µA static current at +25°C.

Technical Context

This device implements the Boolean function Y = A • B with an open-drain output stage, enabling wired-OR bus configurations and bidirectional level translation across voltage domains. Its Schmitt-trigger inputs tolerate slow-rising signals and reject noise, while the IOFF circuit blocks back-current during partial power-down states.

Propagation delay ranges from 0.9 ns (typical, 3.3 V, CL = 5 pF) to 2.3 ns (typical, 3.3 V, CL = 30 pF), with input transition rate support up to 200 ns/V. Power dissipation capacitance is fixed at 6.1 pF (3.3 V), and input capacitance is 1.5 pF - critical for high-speed low-load digital interfacing.

Key Specifications

Pinout & Package

X1-DFN1010-6 package: 1.0 mm × 1.0 mm × 0.5 mm body, 0.35 mm pad pitch, no leads, bottom thermal pad, RoHS-compliant and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input AND gate with open-drain output applications.

Compared with SN74LVC1G09DBVR and 74LVC1G09GW,125, the 74AUP1G09FW5-7 uniquely supports 0.8 V operation, IOFF, and Schmitt inputs - making it the only choice for battery-critical, multi-rail, noise-prone portable designs requiring guaranteed low-leakage shutdown behavior.

Availability

74AUP1G09FW5-7 is available at Aetrix Electronics and suitable for mobile sensor interfaces, I²C bus expansion, low-power wake-up logic, and USB-C CC line control requiring stable component supply across extended product lifecycles.

Supply support for 74AUP1G09FW5-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability, low-power, and small-footprint solutions for consumer, computing, and industrial markets.

The 74AUP logic family targets ultra-low-power portable electronics, delivering sub-1 µA static current and wide-VCC operation to extend battery life in smartphones, wearables, and IoT endpoints.

FAQ

Can 74AUP1G09FW5-7 operate reliably at 0.85 V?

Yes. The device is fully characterized down to 0.8 V, with propagation delay of 13.5 ns (typical, CL = 5 pF) and VOL ≤ 0.11 V at IOL = 20 µA. All DC parameters including VIH/VIL and ICC remain valid across the entire 0.8–3.6 V range per DS35151 Rev. 5–2.

What is the maximum sink current capability at 1.2 V supply?

At VCC = 1.2 V, the device delivers 1.1 mA sink current with VOL ≤ 0.3 × VCC (≤ 0.36 V), verified across –40°C to +125°C. This is specified in Table 5 of the datasheet under Recommended Operating Conditions.

Is the NC pin (Pin 6) required to be grounded?

No. Pin 6 is internally unconnected and must remain floating or be left unbonded per Diodes' AP02002 layout guidance. Grounding it may cause unintended parasitic coupling or violate thermal pad clearance rules in the X1-DFN1010-6 footprint.

Does the Schmitt-trigger input affect propagation delay symmetry?

No. The Schmitt action applies only to input threshold behavior (VIH/VIL hysteresis); propagation delay tPD is measured between input 50% crossing and output 50% crossing, and remains symmetric for rising/falling edges per Figure 1 test setup in the datasheet.