Nexperia USA Inc. 74AUP1G09GM,132

Overview

74AUP1G09GM,132 from Nexperia is a single 2-input AND gate with open-drain output, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, supports 5 pF load propagation delay as low as 0.8 ns (VCC = 3.0–3.6 V), and is qualified for automotive-grade thermal range. It serves in level-shifting I²C bus pull-up control and low-power sensor interface logic.

For engineers reviewing the 74AUP1G09GM,132 datasheet, 74AUP1G09GM,132 pinout, 74AUP1G09GM,132 application, or 74AUP1G09GM,132 equivalent, key selection criteria include open-drain drive strength at 3.0 V (VOL ≤ 0.50 V @ 4.0 mA), input hysteresis enabling robust noise immunity on slow-rising signals, IOFF leakage < ±0.75 μA during power-down, and XSON6 (SOT886) package compatibility with 0.5 mm profile for space-constrained PCBs.

Technical Context

This device implements a single 2-input AND function with true open-drain output-no internal pull-up-requiring external termination. Schmitt-trigger inputs provide ≥0.3×VCC hysteresis (e.g., 0.9 V min at VCC = 3.0 V), enabling reliable operation with slow-edge microcontroller GPIO or noisy sensor outputs.

The IOFF circuit actively disables output terminals when VCC = 0 V, limiting backflow current to ±0.75 μA even with inputs or outputs biased to 3.6 V. It complies with JEDEC standards JESD8-12 through JESD8C across its full 0.8–3.6 V VCC range and is characterized from −40 °C to +125 °C.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad not present; side-wettable flanks not included; RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input open-drain AND gate applications.

Compared with 74LVC1G09GW,125, the 74AUP1G09GM,132 offers superior noise immunity and lower power for sub-1.8 V systems; compared with SN74LVC1G09DBVR, it delivers 30 % smaller footprint and 30 % lower ICC, making it optimal for miniaturized, battery-sensitive designs.

Availability

74AUP1G09GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus level-shifting, low-power wake-up logic, and configurable system reset arbiters requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G09GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in consumer, industrial, and automotive applications.

The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained systems requiring sub-microamp static current, wide VCC flexibility, and robust IO behavior-including IOFF and Schmitt-trigger inputs-for sensor hubs, wearables, and smart infrastructure.

FAQ

Can the 74AUP1G09GM,132 drive a 10 kΩ pull-up resistor on a 3.3 V I²C bus?

Yes. With VOL ≤ 0.50 V at 4.0 mA sink current and typical output resistance < 125 Ω, it fully satisfies I²C Standard Mode (100 kHz) requirements when paired with a 10 kΩ pull-up. The open-drain output ensures bus arbitration compatibility and avoids contention during multi-master operation.

Does the Schmitt-trigger input eliminate the need for external RC filtering on a mechanical switch input?

Yes-within limits. The ≥0.3×VCC hysteresis (e.g., ~1.0 V at 3.3 V) suppresses bounce-induced false triggers up to ~100 μs duration. For switches with >200 μs bounce or high EMI environments, a 100 nF capacitor remains recommended, but the gate reduces required capacitance by 50 % versus non-Schmitt logic.

What is the maximum capacitive load the 74AUP1G09GM,132 can drive while maintaining <10 ns propagation delay?

At VCC = 3.3 V, the device achieves tpd ≤ 10 ns with CL ≤ 30 pF (tpd = 9.1 ns max). This includes probe/jig capacitance; PCB trace capacitance should be limited to ≤15 pF for margin. Exceeding 30 pF increases delay nonlinearly and may degrade VOL under heavy sink conditions.

How does IOFF behavior differ between 74AUP1G09GM,132 and standard 74AUP1G09 variants without IOFF?

The 74AUP1G09GM,132's IOFF circuit actively disables output drivers when VCC = 0 V, limiting leakage to ±0.75 μA. Non-IOFF variants allow uncontrolled back-current flow through parasitic diodes, risking damage or logic corruption in partial-power-down systems-making this variant essential for hot-plug or multi-rail sequenced designs.