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Nexperia USA Inc. 74AUP1G09GW,125

Part No.:
74AUP1G09GW,125
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
5-TSSOP, SC-70-5, SOT-353
Datasheet:
Aetrix74AUP1G09GW,125.pdf
Description:
IC GATE AND 1CH 2-INP 5TSSOP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:364

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Product details

Overview

74AUP1G09GW,125 from Nexperia is a single 2-input AND gate with open-drain output, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, supports −40 °C to +125 °C ambient, and features <10% VCC overshoot/undershoot. It serves as a level-shifting logic interface in low-power I²C bus pull-up control and sensor signal conditioning circuits.

For engineers reviewing the 74AUP1G09GW,125 datasheet, 74AUP1G09GW,125 pinout, 74AUP1G09GW,125 application, or 74AUP1G09GW,125 equivalent, key selection criteria include open-drain drive strength at 3.0 V (VOL ≤ 0.45 V @ 4 mA), input hysteresis for noisy environments, IOFF leakage (<±0.75 μA at VCC = 0 V), and TSSOP5 package compatibility with high-density PCB layouts.

Technical Context

This device implements a single 2-input AND function with true open-drain output-no internal pull-up-requiring external termination. Its Schmitt-trigger inputs provide ≥0.3×VCC hysteresis (e.g., 0.9 V at 3.0 V VCC), enabling robust operation with slow-rising signals from microcontrollers or analog comparators.

The IOFF circuit actively disables the output when VCC = 0 V, limiting backflow current to ±0.75 μA and preventing bus contention during partial power-down sequences in mixed-voltage systems such as battery-backed real-time clocks or modular sensor nodes.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage 0.8 V to 3.6 V - enables direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters.
Max ICC 0.9 μA at −40 °C to +125 °C - ensures sub-1 μA static power in always-on monitoring circuits.
VOL @ 4 mA ≤0.45 V at VCC = 3.0 V - guarantees strong low-state drive into standard 3.3 V I²C bus loads (e.g., 2.2 kΩ pull-up).
Input Hysteresis ≥0.3×VCC - rejects noise up to 900 mV on 3.0 V inputs, eliminating need for external RC filtering.
IOFF Leakage ±0.75 μA at VCC = 0 V - prevents >1 μA backfeed current into powered-down subsystems, meeting JESD78 Class II latch-up immunity.
Propagation Delay 0.8 ns to 4.9 ns (CL = 5 pF, VCC = 3.0–3.6 V) - supports >100 MHz toggle rates in clocked enable paths.
ESD Rating HBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without protection diodes.

Pinout & Package

TSSOP5 plastic thin shrink small outline package (SOT353-1); 5 leads; body width 1.25 mm; 0.65 mm pitch; exposed pad not present.

Pin Circuit Role Design Meaning
1 B Second logic input; Schmitt-triggered; tolerant of slow edges and overvoltage up to 3.6 V.
2 A Primary logic input; identical electrical behavior to Pin 1; dual-input AND function requires both HIGH to assert output.
3 GND Ground reference for all internal circuitry and IOFF control; must be connected before VCC for safe power sequencing.
4 Y Open-drain output; sinks current only; requires external pull-up to define HIGH level; compatible with mixed-voltage buses.
5 VCC Supply voltage input; powers internal logic and IOFF circuitry; IOFF activates automatically when VCC = 0 V.

Key Features

Feature Design Value
Wide VCC range 0.8 V to 3.6 V enables drop-in use across ultra-low-voltage IoT sensors (1.2 V) and industrial 3.3 V controllers.
Schmitt-trigger inputs Input hysteresis ≥0.3×VCC eliminates false triggering from EMI or RC-filtered signals in motor-control feedback paths.
IOFF partial power-down Output disabled and leakage limited to ±0.75 μA when VCC = 0 V - critical for hot-swap and battery-backup system reliability.
Overvoltage-tolerant inputs Accepts up to 3.6 V regardless of VCC setting - allows interfacing with 3.3 V peripherals while operating at 1.8 V core voltage.
Low dynamic noise Overshoot/undershoot <10% of VCC reduces crosstalk in high-density routing and meets CISPR-25 Class 4 EMC requirements.

Applications

I²C Bus Level Translation Low-Power Sensor Interface

Use Scenario: Bidirectional signal translation between 1.8 V microcontroller and 3.3 V EEPROM on shared I²C bus.

IC Role / Device Role / Timing Role: Open-drain AND gate acts as active-low enable for pull-up switching, isolating voltage domains while preserving bus arbitration.

Use Value: Eliminates discrete MOSFET level shifters; IOFF prevents backfeed when MCU enters deep sleep (VCC = 0 V).

Use Scenario: Wake-up signal conditioning from analog motion detector with slow-rising output edge.

IC Role / Device Role / Timing Role: Schmitt-trigger AND gate debounces and synchronizes noisy analog comparator output before MCU interrupt input.

Use Value: Reduces false wake-ups by >95% vs. standard CMOS input; consumes <1 μA in standby, extending coin-cell life.

Modular Power Sequencing Industrial Serial Bus Isolation

Use Scenario: Controlled enable of downstream 2.5 V LDO based on master 3.3 V rail status and safety interlock signal.

IC Role / Device Role / Timing Role: Dual-input AND gate combines power-good and interlock signals to drive LDO EN pin via open-drain configuration.

Use Value: Ensures zero current flow into EN pin during main rail shutdown; IOFF blocks reverse current from 2.5 V domain.

Use Scenario: Galvanically isolated RS-485 transceiver control line buffering with fail-safe biasing.

IC Role / Device Role / Timing Role: Open-drain output drives optocoupler LED anode; A/B inputs receive local controller and fault status signals.

Use Value: Enables OR-fault detection (any input LOW forces output LOW); VOL ≤0.45 V ensures full LED turn-on at 3.0 V.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input open-drain AND gate applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC1G09DBVR Wider VCC (1.65–5.5 V); no Schmitt inputs; higher ICC (10 μA typ); no IOFF. Lacks hysteresis and power-down isolation - unsuitable for noisy sensor interfaces or partial power-down systems. Select only if operating exclusively above 1.65 V and no IOFF or Schmitt functionality is required.
74LVC1G09GW,125 Same TSSOP5 package; identical pinout; but no Schmitt inputs and no IOFF; higher VOL (0.55 V @ 4 mA). Cannot replace in noise-prone or hot-swap designs; marginally higher VOL may violate I²C high-noise margin at 3.3 V. Use only in benign, fully powered environments where cost is prioritized over robustness and power control.

Compared with SN74LVC1G09DBVR and 74LVC1G09GW,125, the 74AUP1G09GW,125 uniquely delivers sub-1 μA static power, Schmitt noise immunity, and IOFF-enabled bus isolation - making it the sole choice for battery-critical, mixed-voltage, or safety-monitored systems.

Availability

74AUP1G09GW,125 is available at Aetrix Electronics and suitable for I²C bus translation, low-power sensor wake-up, modular power sequencing, and industrial serial bus isolation requiring stable component supply across automotive, medical, and industrial temperature grades.

Supply support for 74AUP1G09GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume electronics.

The 74AUP (Advanced Ultra Low Power) product line targets battery-powered and energy-sensitive applications, emphasizing nanowatt static power, wide voltage operation, and robust signal integrity under real-world noise and thermal conditions.

FAQ

Can 74AUP1G09GW,125 drive a 10 kΩ pull-up resistor on a 3.3 V I²C bus?

Yes. With VOL ≤ 0.45 V at 4 mA sink current and typical output low impedance <100 Ω, it pulls the bus below 0.4 V even with 10 kΩ pull-up at 3.3 V - well within I²C Standard Mode (≤0.4 V) and Fast Mode (≤0.4 V) specifications. The open-drain structure inherently supports wired-AND bus topology.

Does the IOFF feature require external control or enable pins?

No. IOFF is fully automatic and requires no external signals. When VCC drops to 0 V, internal circuitry disables the output stage and limits leakage to ±0.75 μA regardless of input or output voltage levels - ensuring passive, fail-safe isolation during power loss or hot-swap events.

What is the minimum input rise time this device can reliably handle?

With Schmitt-trigger inputs providing ≥0.3×VCC hysteresis, the device tolerates input rise/fall times up to 200 ns/V (per datasheet Table 6). At 3.0 V VCC, this allows clean switching with edges as slow as 600 ns - sufficient for RC-filtered signals from thermistors, potentiometers, or legacy microcontroller GPIOs.

Is the TSSOP5 package (SOT353-1) lead-free and RoHS-compliant?

Yes. The 74AUP1G09GW,125 uses a lead-free, halogen-free, RoHS-compliant TSSOP5 package (SOT353-1) with matte tin plating. It meets JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) and qualifies for standard reflow soldering profiles including IPC/JEDEC J-STD-020 Rev. E.

74AUP1G09GW,125 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
5-TSSOP, SC-70-5, SOT-353
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
AND Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
Open Drain
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
-, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
12.7ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
5-TSSOP

74AUP1G09GW,125 FAQ

1.How can I place an order for 74AUP1G09GW,125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G09GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of 74AUP1G09GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G09GW,125 is usually 5 days.

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5.How can I obtain technical support or documentation for 74AUP1G09GW,125?

For technical support, including 74AUP1G09GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G09GW,125 requirements.

6.How does Aetrix verify that 74AUP1G09GW,125 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G09GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G09GW,125 meets industry standards.

7.What is the process for return or replacement of 74AUP1G09GW,125?

All 74AUP1G09GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G09GW,125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G09GW,125 part is unused and in its original packaging.

Return procedure for 74AUP1G09GW,125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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