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Nexperia USA Inc. 74AUP1G09GX,125

Part No.:
74AUP1G09GX,125
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
4-XFDFN Exposed Pad
Datasheet:
Aetrix74AUP1G09GX,125.pdf
Description:
IC GATE AND 1CH 2-INP 5X2SON
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Payment:
Payment
Shipping:
Shipping

Inventory:10,000

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Product details

Overview

74AUP1G09GX,125 from Nexperia is a single 2-input AND gate with open-drain output, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates from 0.8 V to 3.6 V, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, supports 5 pF load propagation delay as low as 0.8 ns (VCC = 3.0–3.6 V), and is housed in SOT1226-3 (X2SON5) package. It enables level-shifting I²C bus pull-ups and low-power sensor interface logic in space-constrained industrial controllers.

For engineers reviewing the 74AUP1G09GX,125 datasheet, 74AUP1G09GX,125 pinout, 74AUP1G09GX,125 application, or 74AUP1G09GX,125 equivalent, key selection criteria include open-drain drive strength at sub-1-V operation, IOFF leakage under partial power-down, Schmitt-trigger hysteresis for noisy sensor inputs, and thermal-enhanced X2SON5 footprint compatibility with automated optical inspection.

Technical Context

This device implements a single 2-input AND function with true open-drain output-no internal pull-up-requiring external termination. Its Schmitt-trigger inputs provide ≥0.3×VCC hysteresis across 0.8–3.6 V supply, enabling robust operation with slow-rising signals from microcontroller GPIOs or analog comparators.

The IOFF circuit actively disables output leakage when VCC = 0 V, limiting power-off current to ±0.75 μA (max) while allowing input/output pins to tolerate up to 3.6 V regardless of VCC state-critical for hot-swap and multi-rail system interconnects.

Key Specifications

ParameterValue and Actual Design Meaning
Logic Function2-input AND with open-drain output; requires external pull-up for HIGH assertion
Supply Voltage Range0.8 V to 3.6 V; supports direct interfacing with 0.9-V I/O domains and 3.3-V systems
Max ICC (−40°C to +125°C)1.4 μA; enables always-on status monitoring without measurable battery drain
tpd @ CL = 5 pF, VCC = 3.3 V0.8 ns (min) to 4.9 ns (max); sufficient for >100 MHz clock domain bridging
VOL @ IO = 4 mA, VCC = 3.0 V≤0.50 V; ensures clean LOW-level recognition by 3.3-V CMOS receivers
IOFF Leakage (VCC = 0 V)±0.75 μA; prevents backfeed current during partial system shutdown
Input Hysteresis≥0.3×VCC; rejects noise spikes on long traces or unshielded sensor lines

Pinout & Package

SOT1226-3 (X2SON5): 5-terminal, no-lead, thermally enhanced plastic package; body dimensions 0.8 × 0.8 × 0.32 mm; pin 1 index located at lower-left corner below marking code 'p9'.

Pin/TerminalCircuit RoleDesign Meaning
1 - BData inputSecond logic input; Schmitt-triggered, overvoltage-tolerant to 3.6 V independent of VCC
2 - AData inputPrimary logic input; identical electrical behavior to Pin 1
3 - GNDGround reference0 V return path; must be low-impedance for stable IOFF and VOL performance
4 - YOpen-drain outputActive-LOW sink only; requires external pull-up resistor for HIGH-level assertion
5 - VCCSupply voltageCore power rail; powers internal logic and enables IOFF control; decoupling capacitor required

Key Features

FeatureDesign Value
Ultra-low static powerICC ≤ 1.4 μA over full temperature range enables battery-backed real-time status latching
IOFF partial power-downBlocks backflow current when VCC = 0 V, supporting live insertion into powered backplanes
Schmitt-trigger inputsHysteresis ≥0.3×VCC eliminates chatter on slow or noisy signals from mechanical switches or analog sensors
Overvoltage-tolerant I/OInputs/outputs withstand 3.6 V regardless of VCC state-enables safe level translation between 1.2-V and 3.3-V domains
X2SON5 thermal enhancement0.32-mm height and exposed die pad improve heat dissipation in dense PCB layouts

Applications

Industrial Sensor InterfaceI²C Bus Level Shifting

Use Scenario: Connecting 1.8-V digital Hall-effect sensor outputs to a 3.3-V microcontroller GPIO with noise immunity.

IC Role / Device Role / Timing Role: Logic-level translator and noise filter; AND gate combines two sensor alerts before routing to MCU interrupt line.

Use Value: Schmitt-trigger inputs reject EMI-induced glitches; open-drain output allows shared 3.3-V pull-up with other I²C devices.

Use Scenario: Extending an I²C bus between 1.2-V SoC and 3.3-V EEPROM using standard pull-up resistors.

IC Role / Device Role / Timing Role: Bidirectional voltage translator element; configured as wired-AND node with external pull-ups on both sides.

Use Value: IOFF prevents current leakage when SoC is powered down while EEPROM remains active; 0.8 ns tpd preserves I²C timing margins.

Low-Power Status MonitoringHot-Swappable Module Detection

Use Scenario: Monitoring standby power rail presence in a battery-powered medical monitor with <1 μA quiescent budget.

IC Role / Device Role / Timing Role: Enable gate for system wake-up logic; output drives enable pin of LDO only when both VBAT and EN signals are asserted.

Use Value: ICC ≤ 1.4 μA ensures no measurable impact on 10-year battery life; open-drain output interfaces directly with LDO enable threshold.

Use Scenario: Detecting insertion of a peripheral module into a powered carrier board without disrupting main system operation.

IC Role / Device Role / Timing Role: Hot-swap presence detector; inputs sense module ID pins, output asserts 'READY' signal after power stabilization.

Use Value: IOFF blocks backfeed from module's 3.3-V rail into carrier's 1.8-V logic during insertion transient; overvoltage tolerance avoids clamping diode conduction.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input AND gate applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
74LVC1G09GW,125Higher ICC (max 10 μA), no Schmitt-trigger inputs, same open-drain outputLacks noise immunity on slow-rising signals; unsuitable for unconditioned sensor inputsSelect when cost sensitivity outweighs noise rejection needs and supply is stable ≥1.65 V
SN74LVC1G09DBVRSame logic function but SOT-23-5 package; higher thermal resistance (210 K/W vs. 180 K/W)Less suitable for high-density layouts requiring minimal footprint and thermal reliefPrefer only if legacy SOT-23 assembly infrastructure exists and thermal margin >15 °C is available

Compared with 74LVC1G09GW,125 and SN74LVC1G09DBVR, the 74AUP1G09GX,125 uniquely combines sub-1-μA static current, Schmitt-trigger noise immunity, and X2SON5 thermal efficiency-making it optimal for always-on, space-constrained, and mixed-voltage industrial edge nodes.

Availability

74AUP1G09GX,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus extension, low-power status monitoring, and hot-swappable module detection requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G09GX,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient components for automotive, industrial, mobile, and computing applications.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power, wide-VCC-range digital interfacing in battery-operated and thermally constrained systems-designed specifically for robust signal conditioning where supply rails vary or coexist.

FAQ

Can 74AUP1G09GX,125 drive a 10-kΩ pull-up resistor at 3.3 V while maintaining VOL ≤ 0.4 V?

Yes. At VCC = 3.0 V and IO = 4.0 mA, VOL is guaranteed ≤0.50 V. With a 10-kΩ pull-up, output current is ~0.33 mA-well within the 4 mA test condition-and typical VOL drops to ~0.05 V, ensuring reliable LOW-level recognition by 3.3-V CMOS receivers.

Does the IOFF feature activate automatically when VCC is removed?

Yes. IOFF is intrinsic circuitry-not software-controlled. When VCC = 0 V, the output stage is disabled and IOFF leakage is limited to ±0.75 μA maximum, preventing backflow current even if inputs or outputs are biased to 3.6 V.

What is the minimum recommended VCC for guaranteed operation with 1.8-V inputs?

0.9 V. Per JEDEC JESD8-11 compliance and Table 6, VIH(min) = 0.65×VCC applies for VCC = 0.9–1.65 V. To recognize 1.8-V inputs as HIGH, VCC must be ≥1.8 V ÷ 0.65 ≈ 2.77 V-so 2.8 V is the practical minimum for 1.8-V input compatibility.

Is the X2SON5 package compatible with standard reflow profiles for lead-free soldering?

Yes. SOT1226-3 (X2SON5) is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 and supports peak reflow temperatures up to 260 °C. Its 0.32-mm profile and thermal pad design ensure uniform heating and void-free solder joints under standard Pb-free profiles.

74AUP1G09GX,125 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
4-XFDFN Exposed Pad
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
AND Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
Open Drain
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
-, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
12.7ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
5-X2SON (0.80x0.80)

74AUP1G09GX,125 FAQ

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Please submit a Request for Quotation (RFQ) for 74AUP1G09GX,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of 74AUP1G09GX,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G09GX,125 is usually 5 days.

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5.How can I obtain technical support or documentation for 74AUP1G09GX,125?

For technical support, including 74AUP1G09GX,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G09GX,125 requirements.

6.How does Aetrix verify that 74AUP1G09GX,125 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G09GX,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G09GX,125 meets industry standards.

7.What is the process for return or replacement of 74AUP1G09GX,125?

All 74AUP1G09GX,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G09GX,125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G09GX,125 part is unused and in its original packaging.

Return procedure for 74AUP1G09GX,125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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