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Diodes Incorporated 74AUP1G09SE-7

Part No.:
74AUP1G09SE-7
Manufacturer:
Diodes Incorporated
Category:
Gates and Inverters
Package:
5-TSSOP, SC-70-5, SOT-353
Datasheet:
Aetrix74AUP1G09SE-7.pdf
Description:
IC GATE AND 1CH 2-INP SOT353
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:8,250

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Product details

Overview

74AUP1G09SE-7 from Diodes Incorporated is a single 2-input positive AND gate with open-drain output, designed for ultra-low-power logic interfacing in battery-powered systems. It operates across 0.8V–3.6V supply, delivers 4mA output drive at 3.0V, features IOFF partial power-down protection, and includes Schmitt-trigger inputs with ~250mV hysteresis at 3.0V for noise immunity in noisy environments.

For engineers reviewing the 74AUP1G09SE-7 datasheet, 74AUP1G09SE-7 pinout, 74AUP1G09SE-7 application, or 74AUP1G09SE-7 equivalent, key selection criteria include open-drain compatibility with I²C/1-wire buses, sub-1µA static current, wide VCC range for multi-rail voltage translation, and validated IOFF behavior during system sleep states.

Technical Context

This AUP-family device implements standard Boolean AND logic (Y = A • B) with an open-drain output requiring an external pull-up resistor. Its IOFF circuit actively disables output leakage when VCC = 0V, preventing back-current flow into powered-down subsystems - critical for mixed-voltage domain isolation.

Schmitt-trigger inputs provide robust switching with defined hysteresis (~250mV at VCC = 3.0V), enabling reliable operation with slow-rising signals (e.g., RC-filtered reset lines or mechanical switch debouncing). Propagation delay ranges from 0.9ns (typ, 3.3V, CL = 5pF) to 27ns (0.8V, CL = 30pF), scaling predictably with supply and load.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage 0.8V to 3.6V - supports direct interface with 1.2V, 1.8V, 2.5V, and 3.3V logic domains without level shifters.
Output Type Open-drain - enables wired-AND bus topology, I²C-compatible signaling, and flexible pull-up voltage selection (up to 5.5V).
IOL Drive 4mA at VCC = 3.0V - sufficient to sink standard I²C bus capacitance (400pF) at 100kHz with <1V drop.
ICC Static Current <0.9µA max at +25°C - extends battery life in always-on sensor nodes and wearable standby modes.
IOFF Leakage ±0.5µA max (VI/VO = 0–3.6V) - prevents >1µA backfeed current when host MCU is powered down.
Input Hysteresis ~250mV at VCC = 3.0V - rejects noise spikes up to ±125mV on slow edges (e.g., thermistor-based wake-up signals).
tPD Delay 0.9ns typ (3.3V, CL = 5pF) - meets timing budgets for low-latency enable/control paths in portable audio codecs.

Pinout & Package

SOT353 (2.0mm × 2.0mm × 1.1mm, 0.65mm pitch) - compact leaded package with exposed pad option for thermal relief in space-constrained PCB layouts.

Pin/Terminal Circuit Role Design Meaning
1 (A) Data Input Primary logic input; Schmitt-triggered for noise immunity; VIH/VIL thresholds scale with VCC.
2 (B) Data Input Secondary logic input; identical electrical specs to Pin 1; both inputs tolerate 0–3.6V regardless of VCC.
3 (GND) Ground Reference Return path for all internal logic and output current; must be low-impedance to maintain noise margin.
4 (Y) Open-Drain Output Active-low sinking node; requires external pull-up; supports voltage translation up to 5.5V on Y line.
5 (VCC) Power Supply Core logic supply; IOFF activates when VCC = 0V, disabling Y regardless of A/B state.

Key Features

Feature Design Value
Ultra-low static power ICC < 0.9µA ensures < 3µA total quiescent draw in 3-gate control chains for medical patch sensors.
IOFF partial power-down Blocks >99% of back-current flow when VCC is removed - essential for hot-swap USB-C accessory detection.
Schmitt-trigger inputs 250mV hysteresis at 3.0V eliminates chatter on mechanical switch inputs without external RC filtering.
ESD robustness 2kV HBM / 1kV CDM rating allows direct handling in bench assembly without special ESD controls.
Wide VCC range 0.8–3.6V operation enables single BOM reuse across 1.2V SoC rails and 3.3V peripheral interfaces.

Applications

Mobile Device Power Sequencing I²C Bus Level Translation

Use Scenario: Coordinating power-up order of AP, PMIC, and display driver ICs in smartphones using discrete enable signals.

IC Role / Device Role / Timing Role: AND gate combines two independent reset sources to generate synchronized enable pulse for display power rail.

Use Value: Open-drain output allows shared pull-up to 3.3V while inputs accept 1.2V AP GPIOs - eliminating discrete level shifters.

Use Scenario: Interfacing 1.8V microcontroller I²C pins to 3.3V sensor EEPROM on same bus segment.

IC Role / Device Role / Timing Role: Wired-AND logic element implementing bidirectional data arbitration with external 3.3V pull-ups.

Use Value: Sub-1ns propagation delay preserves I²C timing margins at 400kHz; IOFF prevents bus contention during MCU sleep.

Wearable Sensor Wake-Up Logic Industrial Button Debounce Circuit

Use Scenario: Detecting simultaneous press of two mechanical buttons to trigger secure boot mode in fitness trackers.

IC Role / Device Role / Timing Role: Dual-input AND gate with Schmitt-trigger inputs conditioning noisy tactile switch signals.

Use Value: 250mV hysteresis rejects bounce transients <1ms duration; 0.9µA ICC extends coin-cell life beyond 2 years.

Use Scenario: Generating clean interrupt signal from unfiltered push-button input in programmable logic controllers.

IC Role / Device Role / Timing Role: Positive AND gate combining button closure and system-ready flag before asserting IRQ line.

Use Value: Open-drain output interfaces directly to 5V-tolerant FPGA input; IOFF isolates button circuit during PLC firmware update.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input AND gate applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC1G08DSFR Pure CMOS push-pull output; no IOFF; 1.65–5.5V supply range. Requires external isolation for partial power-down; unsuitable for mixed-voltage bus arbitration. Select when driving high-speed loads (>50MHz) where open-drain delay is unacceptable.
NC7SZ08P5X Push-pull output; lower ICC (0.1µA); no Schmitt inputs; 1.65–5.5V operation. Lacks noise immunity on slow edges; cannot replace 74AUP1G09SE-7 in RC-debounced switch circuits. Prefer for cost-sensitive consumer audio docks where input slew rates exceed 1V/ns.

Compared with SN74LVC1G08DSFR and NC7SZ08P5X, the 74AUP1G09SE-7 uniquely combines open-drain flexibility, sub-1µA quiescent current, and Schmitt-trigger noise rejection - making it irreplaceable in battery-critical, multi-rail, and noisy-switch applications.

Availability

74AUP1G09SE-7 is available at Aetrix Electronics and suitable for mobile device power sequencing, I²C bus level translation, wearable sensor wake-up logic, and industrial button debounce circuits requiring stable component supply across extended product lifecycles.

Supply support for 74AUP1G09SE-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal solutions for power management, signal integrity, and connectivity applications.

The 74AUP logic family targets ultra-low-power portable electronics, emphasizing extended battery life, wide supply voltage tolerance, and robustness in partial-power-down system architectures.

FAQ

Can 74AUP1G09SE-7 drive a 10kΩ pull-up to 5V?

Yes. The open-drain output is rated for 4mA sink current at 3.0V, allowing safe operation with a 10kΩ pull-up to 5V (I = 500µA). Output voltage drop remains below 0.45V per datasheet, ensuring valid logic-low levels for 5V-tolerant receivers.

Does IOFF function when only one supply rail is active?

Yes. IOFF activates whenever VCC = 0V, regardless of input or output voltage. If VCC is disconnected while A/B/Y are biased to 3.3V, the output is electrically isolated - preventing >0.5µA back-current into the powered-down domain.

What is the maximum capacitive load for guaranteed timing performance?

The datasheet specifies switching characteristics up to 30pF. At 3.3V, tPD increases from 0.9ns (5pF) to 2.3ns (30pF). For loads >30pF, propagation delay rises nonlinearly; use a buffer stage if driving >50pF traces or multiple inputs.

Is the Schmitt-trigger hysteresis voltage fixed or supply-dependent?

Hysteresis is supply-dependent: ~250mV at VCC = 3.0V, scaling approximately linearly. At 1.2V, hysteresis drops to ~100mV. This maintains consistent noise margin percentage (±4–5% of VCC) across the full 0.8–3.6V operating range.

74AUP1G09SE-7 Specifications

Product attributes
Attribute value
Manufacturer:
Diodes Incorporated
Series:
74AUP
Package/Case:
5-TSSOP, SC-70-5, SOT-353
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
AND Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
Open Drain
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
-, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
12.7ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
SOT-353

74AUP1G09SE-7 FAQ

1.How can I place an order for 74AUP1G09SE-7 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G09SE-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1G09SE-7 reliable?

The price and inventory of 74AUP1G09SE-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G09SE-7 is usually 5 days.

3.What payment methods are accepted for 74AUP1G09SE-7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G09SE-7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP1G09SE-7?

74AUP1G09SE-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP1G09SE-7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1G09SE-7?

For technical support, including 74AUP1G09SE-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G09SE-7 requirements.

6.How does Aetrix verify that 74AUP1G09SE-7 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G09SE-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G09SE-7 meets industry standards.

7.What is the process for return or replacement of 74AUP1G09SE-7?

All 74AUP1G09SE-7 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G09SE-7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G09SE-7 part is unused and in its original packaging.

Return procedure for 74AUP1G09SE-7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

74AUP1G09SE-7 Tags

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