NXP Semiconductors 74AUP1G11GN,132

Overview

74AUP1G11GN,132 from Nexperia is a single 3-input AND gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤0.9 μA max), IOFF-enabled partial power-down protection, and guaranteed operation from –40 °C to +125 °C in the SOT1115 XSON6 package. It serves as a noise-immune signal combiner in battery-powered sensor interfaces and low-voltage control sequencing.

For engineers reviewing the 74AUP1G11GN,132 datasheet, 74AUP1G11GN,132 pinout, 74AUP1G11GN,132 application, or 74AUP1G11GN,132 equivalent, this device offers verified Schmitt-trigger hysteresis, sub-1 ns propagation delay at 3.3 V (CL = 5 pF), IOFF leakage < ±0.75 μA at VCC = 0 V, and JEDEC-compliant ESD robustness (HBM > 5000 V, CDM > 1000 V).

Technical Context

This device implements standard positive-logic 3-input AND functionality (Y = A · B · C) with Schmitt-trigger input thresholds-VIH ≥ 0.70×VCC and VIL ≤ 0.30×VCC at VCC = 0.8 V-enabling reliable operation with slow-rising signals. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.

Dynamic performance is load- and voltage-dependent: propagation delay ranges from 1.3 ns (typ, VCC = 3.3 V, CL = 5 pF) to 18.9 ns (typ, VCC = 0.8 V, CL = 5 pF). Power dissipation capacitance is 4.1 pF at 3.3 V, supporting precise dynamic power estimation via PD = CPD × VCC² × fi × N.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount design; body dimensions 0.9 mm × 1.0 mm × 0.35 mm; pin 1 index located at lower-left corner beneath marking code "pU".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-input AND gate applications.

Compared with SN74LVC1G11DBVR and 74LVC1G11GW,125, the 74AUP1G11GN,132 uniquely delivers sub-1 μA static current, Schmitt-trigger noise immunity, and IOFF protection-all in a 0.9 × 1.0 mm XSON6 footprint-making it optimal for energy-critical, mixed-voltage, and hot-pluggable designs.

Availability

74AUP1G11GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable medical monitors, automotive body controllers, and battery-powered IoT edge nodes requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G11GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power portable and battery-operated applications, emphasizing minimal static/dynamic power, wide voltage operation, and robustness in thermally demanding environments.

FAQ

Does the 74AUP1G11GN,132 support 0.8 V operation with full timing guarantees?

Yes. The datasheet specifies propagation delay (18.9 ns typ), VIH/VIL thresholds, and output drive (VOH/VOL) across –40 °C to +125 °C at VCC = 0.8 V. All static and dynamic parameters are characterized and guaranteed down to 0.8 V, enabling direct interface with advanced ultra-low-voltage microcontrollers and ASICs.

How does the IOFF feature behave when VCC is ramping or partially powered?

IOFF activates when VCC falls below ~0.2 V, disabling the output stage to prevent back-current flow. During power-up, outputs remain in high-impedance until VCC exceeds the minimum functional threshold (~0.6 V), avoiding bus contention. This behavior is verified per JESD78 Class II latch-up testing and documented in Section 6.2 and Table 7.

Can the Schmitt-trigger inputs accept 3.6 V signals while VCC is at 1.2 V?

Yes. Input pins are overvoltage tolerant to 3.6 V independent of VCC level. At VCC = 1.2 V, VIH is guaranteed ≥ 0.78 V and VIL ≤ 0.36 V, with hysteresis width ≥ 0.15 V-ensuring clean switching even with 3.3 V signals driving into a 1.2 V domain without level translation.

What is the maximum capacitive load the 74AUP1G11GN,132 can drive while maintaining timing specs?

The device is characterized up to CL = 30 pF across all VCC and temperature ranges. At VCC = 3.3 V and Tamb = 25 °C, tpd remains ≤ 6.1 ns (max) with 30 pF load. Driving heavier loads increases delay nonlinearly and may exceed recommended operating conditions; for >30 pF, buffer staging or layout optimization is advised.