Nexperia USA Inc. 74AUP1G125GM,115

Overview

74AUP1G125GM,115 from Nexperia is a single low-power 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply range, delivering ICC ≤ 1.4 μA (max) at −40 °C to +125 °C, tpd ≤ 4.4 ns (VCC = 3.0–3.6 V, CL = 5 pF), and IOFF-enabled partial power-down protection. It is used in space-constrained I/O expansion and level-shifting interfaces in portable industrial sensors and battery-powered MCU peripheral buses.

For engineers reviewing the 74AUP1G125GM,115 datasheet, 74AUP1G125GM,115 pinout, 74AUP1G125GM,115 application, or 74AUP1G125GM,115 equivalent, key selection criteria include ultra-low static current, guaranteed 3-state behavior under partial power-down, Schmitt-trigger noise immunity on A and OE inputs, and compatibility with 0.8 V logic systems.

Technical Context

This device implements a single non-inverting buffer with active-low 3-state output control (OE). Its Schmitt-trigger inputs tolerate slow-rising/falling signals and provide hysteresis of typically 0.3 V at VCC = 3.3 V, enabling robust operation in noisy environments. The IOFF circuit actively disables output leakage when VCC = 0 V, preventing backflow current in mixed-voltage or hot-swap systems.

It supports JEDEC-compliant voltage standards across five VCC ranges (JESD8-12 through JESD8-B), ensuring interoperability with legacy and next-gen logic families. Dynamic performance scales predictably with supply voltage and load capacitance - propagation delay ranges from 20.6 ns at 0.8 V/5 pF to 1.4 ns at 3.6 V/5 pF - without requiring external biasing or termination.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flanks not present; thermal pad absent.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar buffer/line driver applications.

Compared with 74LVC1G125GW,125 and SN74AUP1G125DBVR, the 74AUP1G125GM,115 delivers 86% lower max ICC, supports 0.8 V operation, and fits in 42% less board area - making it optimal for battery-critical and space-constrained embedded systems where power sequencing and layout density are primary constraints.

Availability

74AUP1G125GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, and automotive body electronics requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP1G125GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power, wide-VCC digital interfacing - specifically engineered for battery-operated, thermally constrained, and mixed-voltage embedded systems demanding minimal quiescent current and robust noise immunity.

FAQ

Can 74AUP1G125GM,115 drive a 50 pF load reliably?

No - the datasheet specifies dynamic characteristics only up to CL = 30 pF. At 50 pF, propagation delay increases nonlinearly (e.g., tpd ≈ 9.2 ns at VCC = 3.3 V), and output rise/fall times degrade beyond design margins. For >30 pF loads, add series termination or use a higher-drive buffer like 74AUP2G125.

Is the n.c. pin on SOT886 (pin 4) required to be grounded?

No - pin 4 is internally unconnected and electrically isolated. It may be left floating per Nexperia's layout guidelines; grounding is optional and provides no electrical benefit but may improve mechanical anchoring during reflow.

Does the IOFF feature work when OE is floating?

No - IOFF activates only when VCC = 0 V *and* OE is driven to a defined logic state (HIGH or LOW). A floating OE causes undefined output behavior and disables IOFF protection; OE must be actively pulled HIGH or LOW via external resistor or controller GPIO.

What is the maximum recommended PCB trace length for 100 MHz operation?

For reliable 100 MHz operation (period = 10 ns), trace length should be ≤15 cm when routed over solid ground plane with controlled 50 Ω impedance. Beyond this, signal integrity degrades due to reflections and tpd variation; use on-die termination or external series resistors for longer runs.