Nexperia USA Inc. 74AUP1G125GM-Q100X
- Part No.:
- 74AUP1G125GM-Q100X
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G125GM-Q100X.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:4,668
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Product details
Overview
74AUP1G125GM-Q100 from Nexperia is a single-channel automotive-grade 3-state buffer/line driver with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at +125 °C), IOFF-enabled partial power-down protection, and AEC-Q100 Grade 1 qualification for engine control and body electronics applications.
For engineers reviewing the 74AUP1G125GM-Q100 datasheet, 74AUP1G125GM-Q100 pinout, 74AUP1G125GM-Q100 application, or 74AUP1G125GM-Q100 equivalent, this device is selected for low-voltage signal buffering in space-constrained automotive modules where input noise immunity, rail-to-rail compatibility, and zero backflow current during power sequencing are critical design requirements.
Technical Context
This device implements a non-inverting buffer with active-low 3-state output enable (OE), enabling bidirectional bus isolation. Its Schmitt-trigger inputs provide hysteresis (≥0.3×VCC) to reject slow-rising or noisy signals common in automotive harness environments.
The IOFF circuit ensures output remains high-impedance and leakage-limited (±0.75 μA) when VCC = 0 V, preventing destructive back-currents during hot-swap or multi-rail power-down sequences - a key requirement for ASIL-B compliant subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Max ICC (Tamb = +125 °C) | 1.4 μA - enables always-on monitoring circuits with <1 μW quiescent power at 1.8 V |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - meets AEC-Q100 partial power-down current limits for safe inter-rail isolation |
| Propagation Delay (VCC = 3.3 V, CL = 15 pF) | 4.4 ns - sufficient for ≤100 MHz digital control signaling in ECU timing paths |
| Input Hysteresis (VIH − VIL) | ≥0.3×VCC - rejects >100 ns noise pulses on long PCB traces or cable-connected sensors |
| ESD Robustness | HBM >5000 V, CDM >1000 V - exceeds automotive system-level ESD immunity requirements per ISO 10605 |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood placement in engine management and transmission control units |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886), 1.0 × 1.45 × 0.5 mm body, no leads, 6 terminals, thermal pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable (active-low) | Drives Y high-impedance when LOW; enables bus sharing and power-gated subsystems |
| 2 (A) | Data Input | Schmitt-trigger input accepts 0–3.6 V signals; tolerant of slow edges and floating conditions |
| 3 (GND) | Ground Reference | 0 V reference for all I/O and internal logic; must be low-inductance connection for noise immunity |
| 4 (n.c.) | No Connect | Internally unconnected terminal; left floating per design - no external tie required |
| 5 (VCC) | Supply Voltage | Primary power rail; decoupling capacitor (100 nF) required within 2 mm for stable operation |
| 6 (Y) | Buffered Output | Non-inverting 3-state output; sinks/sourcing up to ±20 mA; compatible with 50 Ω transmission lines |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable signal acquisition from noisy sources (e.g., Hall-effect sensors, switch contacts) without external hysteresis circuitry |
| IOFF partial power-down | Prevents damaging back-current flow when VCC is off but A or Y remain biased - essential for modular ECU architectures |
| AEC-Q100 Grade 1 qualification | Validated for automotive use across −40 °C to +125 °C ambient, including temperature cycling and HTOL stress testing |
| Ultra-low dynamic power | CPD = 4.2 pF at 3.3 V enables sub-μW switching power at 1 MHz - extends battery life in always-on modules |
| Wide voltage compatibility | Single device interfaces 0.8 V FPGA I/O, 1.8 V microcontrollers, and 3.3 V CAN transceivers without voltage translation |
Applications
| Engine Control Unit (ECU) Signal Conditioning | Body Control Module (BCM) Bus Isolation |
|---|---|
Use Scenario: Buffering crankshaft position sensor signals before ADC sampling in gasoline/diesel ECUs. IC Role / Device Role / Timing Role: Signal integrity conditioner with Schmitt-trigger input rejecting EMI from ignition coils and injectors. Use Value: Eliminates need for external RC filters and reduces BOM count while maintaining <10 ns timing jitter at 10 kHz sensor frequency. | Use Scenario: Isolating LIN bus transceiver data lines during sleep mode in door module controllers. IC Role / Device Role / Timing Role: 3-state buffer enabling controlled bus release via OE signal synchronized with MCU deep-sleep entry. Use Value: Reduces LIN standby current by 85% versus direct MCU GPIO drive, meeting ISO 14229-3 sleep current targets. |
| Advanced Driver Assistance Systems (ADAS) Camera Interface | Electric Power Steering (EPS) Motor Control Feedback |
Use Scenario: Level-shifting and buffering MIPI CSI-2 clock enable signals between 1.2 V image sensor and 3.3 V SoC. IC Role / Device Role / Timing Role: Voltage-tolerant buffer preserving edge rate integrity across mixed-supply domains. Use Value: Maintains <50 ps skew between parallel camera lanes while supporting 1.2 V to 3.3 V translation without delay variation. | Use Scenario: Isolating resolver-to-digital converter (RDC) feedback signals from motor gate driver ICs during fault shutdown. IC Role / Device Role / Timing Role: Fail-safe 3-state buffer activated by hardware fault signal to disconnect analog feedback path. Use Value: Prevents erroneous torque commands during overcurrent events by enforcing deterministic high-Z state within 3.9 ns (max tdis at 3.3 V). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G125GW-Q100 | Higher ICC (max 40 μA at +125 °C); no Schmitt-trigger inputs; same SOT353-1 package | Lacks noise immunity for long-harness sensor inputs; suitable only for clean-board-level signals | Select when cost sensitivity outweighs noise robustness and ultra-low power is not required |
| SN74AUP1G125DSFR | Industrial grade (−40 °C to +85 °C); identical electrical specs but lacks AEC-Q100 qualification and IOFF test data | Not approved for safety-critical automotive functions; requires additional qualification effort for OEM adoption | Select for non-automotive industrial controls where AEC-Q100 is not mandated |
Compared with 74LVC1G125GW-Q100 and SN74AUP1G125DSFR, the 74AUP1G125GM-Q100 uniquely combines Schmitt-trigger noise rejection, sub-μA quiescent current, and production-proven AEC-Q100 Grade 1 compliance - making it the only drop-in solution for ASIL-B signal conditioning in powertrain and chassis systems.
Availability
74AUP1G125GM-Q100 is available at Aetrix Electronics and suitable for engine control units, body control modules, ADAS camera interfaces, and electric power steering systems requiring stable component supply across extended automotive lifecycles.
Supply support for 74AUP1G125GM-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in automotive-qualified components and advanced packaging.
This device belongs to the 74AUP (Advanced Ultra-low Power) logic family, engineered specifically for energy-efficient automotive signal routing where voltage scalability, noise resilience, and fail-safe power sequencing are mandatory.
FAQ
What is the maximum allowable input voltage when VCC = 0 V?
The device allows input voltages up to 3.6 V regardless of VCC state, verified per JESD78 latch-up testing and absolute maximum ratings. This enables safe "hot insertion" into live buses and eliminates need for external clamping diodes in mixed-power-domain systems.
Does the 74AUP1G125GM-Q100 support 0.8 V logic levels for both input and output?
Yes - VIH minimum is 0.75×VCC (0.6 V at 0.8 V supply), and VOH minimum is VCC − 0.11 V (0.69 V), confirming full 0.8 V logic compatibility. Output drive strength remains ≥1.1 mA at 0.8 V, sufficient for driving 10 pF loads with <10 ns rise time.
How does the IOFF feature behave during VCC ramp-up or ramp-down?
IOFF activates automatically when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.4 V, verified by ΔIOFF measurements. This provides seamless transition through brown-out conditions without glitching or contention on shared buses.
Can the n.c. pin (Pin 4) be used as a thermal pad or grounded for improved thermal performance?
No - Pin 4 is internally unconnected (n.c.), with no bond wire or silicon connection. Grounding or soldering it provides no thermal or electrical benefit and risks mechanical stress on the die attach. Thermal dissipation relies solely on VCC and GND terminations per JEDEC standards.
74AUP1G125GM-Q100X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1G125GM-Q100X FAQ
1.How can I place an order for 74AUP1G125GM-Q100X through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G125GM-Q100X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G125GM-Q100X reliable?
The price and inventory of 74AUP1G125GM-Q100X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G125GM-Q100X is usually 5 days.
3.What payment methods are accepted for 74AUP1G125GM-Q100X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G125GM-Q100X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G125GM-Q100X?
74AUP1G125GM-Q100X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G125GM-Q100X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G125GM-Q100X?
For technical support, including 74AUP1G125GM-Q100X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G125GM-Q100X requirements.
6.How does Aetrix verify that 74AUP1G125GM-Q100X is sourced from the original manufacturer or authorized distributors?
All 74AUP1G125GM-Q100X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G125GM-Q100X meets industry standards.
7.What is the process for return or replacement of 74AUP1G125GM-Q100X?
All 74AUP1G125GM-Q100X units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G125GM-Q100X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G125GM-Q100X part is unused and in its original packaging.
Return procedure for 74AUP1G125GM-Q100X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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