Texas Instruments 74AUP1G126DRLRG4

Overview

74AUP1G126DRLRG4 from Texas Instruments is a single low-power CMOS bus buffer gate with tri-state output, designed for point-to-point signal routing in battery-powered portable systems. It operates across 0.8 V to 3.6 V supply, delivers 4.6 ns max propagation delay at 3.3 V, consumes ≤0.9 µA static current, and supports Ioff partial-power-down mode - enabling safe operation in mixed-voltage SSD, tablet, and wireless peripheral interfaces.

For engineers reviewing the 74AUP1G126DRLRG4 datasheet, 74AUP1G126DRLRG4 pinout, 74AUP1G126DRLRG4 application, or 74AUP1G126DRLRG4 equivalent, key selection criteria include its ultra-low ICC (0.9 µA), 3.6-V I/O tolerance, input-disable capability for floating inputs, and SOT-5X3 package compatibility with space-constrained PCB layouts.

Technical Context

This device implements a non-inverting buffer (Y = A) with active-high output enable (OE), delivering rail-to-rail CMOS logic levels and balanced push-pull drive. Its Ioff circuitry ensures <0.6 µA leakage when VCC = 0 V, enabling hot-insertion and back-drive protection in partial-power-down systems.

The input features hysteresis for noise immunity on slow transitions, and overvoltage-tolerant inputs accept signals up to 4.6 V regardless of VCC. Output disable timing (tdis ≤ 4 ns at 3.3 V, CL = 5 pF) and enable timing (ten ≤ 5.9 ns) support fast bus arbitration in low-latency embedded control paths.

Key Specifications

Pinout & Package

SOT-5X3 (5-pin) package: 1.60 mm × 1.20 mm body, 0.5-mm pitch, ultra-compact footprint optimized for dense portable PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus buffer applications.

Compared with SN74LVC1G126DBVR and 74AHC1G126GW,125, the 74AUP1G126DRLRG4 uniquely combines sub-1-V operation, Ioff-enabled power sequencing safety, and <1-µA static consumption - making it irreplaceable in ultra-low-power portable SSDs and battery-critical wireless accessories.

Availability

74AUP1G126DRLRG4 is available at Aetrix Electronics and suitable for SSD controller interfaces, wireless peripheral hubs, portable audio docks, and tablet power sequencing requiring stable component supply across automotive-grade temperature ranges and long production lifecycles.

Supply support for 74AUP1G126DRLRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for industrial, automotive, and consumer markets.

The AUP family - including the 74AUP1G126DRLRG4 - was engineered specifically for ultra-low-power portable electronics, delivering industry-leading static/dynamic power efficiency across 0.8–3.6 V while maintaining robust signal integrity and mixed-voltage interoperability.

FAQ

What is the maximum propagation delay of the 74AUP1G126DRLRG4 at 3.3 V?

The 74AUP1G126DRLRG4 has a maximum propagation delay (tpd) of 4.6 ns at VCC = 3.3 V ± 0.3 V, CL = 5 pF, and TA = –40°C to +85°C. This value is specified under worst-case process, voltage, and temperature conditions and ensures reliable timing margin in high-speed point-to-point data paths. The 74AUP1G126DRLRG4 achieves this performance while consuming less than 1 µA static current.

Does the 74AUP1G126DRLRG4 support partial-power-down operation?

Yes, the 74AUP1G126DRLRG4 fully supports partial-power-down operation via its Ioff circuitry. When VCC = 0 V, all I/O pins enter a high-impedance state with leakage limited to ≤0.6 µA over temperature. This prevents current backflow into powered-down sections of the system - a critical requirement for hot-pluggable SSD modules and modular tablet accessories where the 74AUP1G126DRLRG4 is commonly deployed.

Can the 74AUP1G126DRLRG4 accept input voltages higher than its supply voltage?

Yes, the 74AUP1G126DRLRG4 features overvoltage-tolerant inputs rated up to 4.6 V, independent of VCC. This allows the 74AUP1G126DRLRG4 to safely interface with 3.3-V or 5-V signals while operating from a lower VCC (e.g., 1.8 V), eliminating external level shifters in mixed-voltage designs such as USB-C accessory detection circuits where the 74AUP1G126DRLRG4 is frequently used.

What is the recommended power-up sequence for the 74AUP1G126DRLRG4?

To ensure the 74AUP1G126DRLRG4 powers up in a known high-impedance state, OE must be held low during VCC ramp-up. TI recommends tying OE to GND through a pulldown resistor (value determined by driver sink capability). This guarantees Y remains tri-stated until firmware asserts OE, preventing bus contention in systems like tablet power sequencers where the 74AUP1G126DRLRG4 controls PMIC enable lines.

Is the 74AUP1G126DRLRG4 compatible with floating input conditions?

Yes, the 74AUP1G126DRLRG4 includes an input-disable feature that allows the A input to float without causing undefined logic states or increased ICC. This behavior is explicitly characterized and supported across the full operating range, making the 74AUP1G126DRLRG4 ideal for flexible PCB designs - such as wireless keyboard variants - where some A inputs may remain unconnected across product SKUs.