Nexperia USA Inc. 74AUP1G126GM,132

Overview

74AUP1G126GM,132 from Nexperia is a single non-inverting 3-state buffer/line driver in XSON6 (SOT886) package, operating from 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, input-disable functionality during OE low, and IOFF circuitry enabling safe partial power-down. Used in low-power I/O expansion, level translation, and bus isolation in portable and battery-powered systems.

For engineers reviewing the 74AUP1G126GM,132 datasheet, 74AUP1G126GM,132 pinout, 74AUP1G126GM,132 application, or 74AUP1G126GM,132 equivalent, key selection criteria include ultra-low ICC (≤0.9 μA max), guaranteed operation down to 0.8 V, -40 °C to +125 °C temperature range, and IOFF-enabled backflow current prevention during power sequencing.

Technical Context

The device implements a single-channel non-inverting logic path with active-high output enable (OE) controlling high-impedance state on Y. Schmitt-trigger action at A and OE inputs ensures robust switching across full VCC range and tolerance to slow edge rates (up to 200 ns/V).

IOFF circuitry activates when VCC = 0 V, limiting VI/VO leakage to ±0.75 μA and preventing damaging backflow current. Input-disable behavior disables A input when OE = LOW, allowing floating input conditions without increased power or undefined states.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); 6-terminal, no-leads; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flank terminals for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar buffer/line driver applications.

Compared with SN74LVC1G126DBVR and 74AUP1G17GW,125, the 74AUP1G126GM,132 uniquely combines sub-μA static current, IOFF protection, and 3-state control in a 1.0 × 1.45 mm footprint - making it optimal for space-constrained, multi-rail, battery-sensitive designs where bus arbitration and power sequencing reliability are critical.

Availability

74AUP1G126GM,132 is available at Aetrix Electronics and suitable for portable medical devices, automotive body electronics, industrial PLC I/O modules, and battery-powered sensor networks requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G126GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient components for automotive, industrial, computing, consumer, and communications markets.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power digital interfacing in battery-operated and thermally constrained applications, emphasizing sub-1 μA static current, wide VCC scalability, and robust power sequencing behavior.

FAQ

What is the minimum VCC required for guaranteed operation of the 74AUP1G126GM,132?

The device is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, VIH is guaranteed ≥0.70 × VCC (≥0.56 V), VOL ≤0.30 × VCC (≤0.24 V), and tPD ≤20.6 ns (CL = 5 pF). This enables direct integration with sub-1 V logic cores and energy-harvesting power supplies without level-shifting.

How does the input-disable feature function when OE is LOW?

When OE = LOW, the A input is internally disconnected from the logic core, eliminating input leakage and preventing undefined states. This allows A to float safely without pull-up/down resistors or risk of increased ICC - critical for systems with unpowered upstream sources or mechanical switch inputs.

Can the 74AUP1G126GM,132 drive a 50 pF load reliably?

While not characterized beyond 30 pF in the datasheet, measured tPD increases linearly with load capacitance. At VCC = 3.3 V and CL = 30 pF, tPD ≤5.8 ns. For CL = 50 pF, extrapolation suggests tPD ≈7.5–8.5 ns - still compatible with ≤100 MHz clocked interfaces. Verify timing margins in final layout with IBIS simulation.

Is the n.c. terminal on pin 5 required to be grounded or left open?

Pin 5 is a true no-connect terminal - internally unconnected and electrically isolated. It must be left floating per Nexperia's assembly guidelines; grounding or tying to VCC introduces risk of solder bridging, thermal stress, or unintended parasitic coupling. No external connection is permitted or recommended.