NXP Semiconductors 74AUP1G126GN,132
- Part No.:
- 74AUP1G126GN,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G126GN,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:150,000
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Product details
Overview
74AUP1G126GN,132 from Nexperia is a single non-inverting 3-state buffer/line driver in XSON6 (SOT1115) package, operating from 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, input-disable functionality during OE low, and IOFF circuitry enabling partial power-down with backflow current prevention. Used in low-power I/O expansion and bus isolation in portable and battery-powered systems.
For engineers reviewing the 74AUP1G126GN,132 datasheet, 74AUP1G126GN,132 pinout, 74AUP1G126GN,132 application, or 74AUP1G126GN,132 equivalent, key selection criteria include ultra-low ICC (≤0.9 μA max), 3-state timing (tdis ≤3.8 ns at 3.6 V), wide VCC range compatibility, and thermal-enhanced XSON6 footprint for high-density PCB layouts.
Technical Context
The device implements a non-inverting logic path with active-high output enable (OE), where OE = LOW forces Y into high-impedance state and disables inputs. Its Schmitt-trigger inputs ensure robust operation across slow-rising signals and full VCC range (0.8–3.6 V), eliminating external hysteresis components.
IOFF circuitry actively isolates I/O terminals when VCC = 0 V, limiting power-off leakage to ±0.75 μA and preventing damaging backflow currents-critical for hot-swap and multi-rail system designs requiring controlled power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Max ICC | 0.9 μA at VCC = 0.8–3.6 V - enables >10-year battery life in always-on sensor nodes |
| Propagation Delay | 1.2–3.9 ns (VCC = 3.0–3.6 V, CL = 5 pF) - suitable for sub-250 MHz data paths in portable interfaces |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - ensures safe interconnection between powered/unpowered subsystems |
| Input Hysteresis | Typ. 100 mV (Schmitt-trigger) - rejects noise up to 100 mV peak-to-peak on slow GPIO lines |
| ESD Rating | HBM >5000 V, CDM >1000 V - meets IEC 61000-4-2 Level 4 for handheld and industrial end equipment |
| Operating Temp | −40 °C to +125 °C - qualified for automotive under-hood and industrial control applications |
Pinout & Package
XSON6 package (SOT1115), 0.9 × 1.0 × 0.35 mm body, 6-terminal no-lead construction with wettable flank for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable Input | Active-HIGH control: OE = HIGH enables Y; OE = LOW disables Y and floats A input |
| 2 (A) | Data Input | Non-inverting input with Schmitt-trigger; accepts 0–3.6 V regardless of VCC |
| 3 (GND) | Ground Reference | 0 V return path for all internal circuitry and I/O; must be low-impedance |
| 4 (Y) | 3-State Output | Drives HIGH/LOW when enabled; high-Z when OE = LOW; supports bus sharing |
| 5 (n.c.) | No Connect | Internally unconnected terminal; must remain floating per datasheet |
| 6 (VCC) | Power Supply | Primary supply rail; decoupling capacitor (100 nF) required within 2 mm |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 0.9 μA across full VCC range - eliminates standby current concerns in energy harvesting systems |
| Input-disable during OE low | A input floats with zero bias current - prevents unintended logic states when bus is tri-stated |
| IOFF partial power-down | Blocks backflow current when VCC = 0 V - enables safe hot-plug of peripheral modules |
| Schmitt-trigger inputs | 100 mV typical hysteresis - tolerates slow edges from RC networks or long traces without oscillation |
| Wide VCC compatibility | Operates from 0.8 V (sub-threshold) to 3.6 V - interoperable with legacy 3.3 V and emerging ultra-low-voltage SoCs |
Applications
| Portable Sensor Hub | Automotive Body Control Module |
|---|---|
Use Scenario: Aggregating analog sensor outputs (temperature, humidity) into a low-power MCU via shared I²C/SPI bus. IC Role / Device Role / Timing Role: Isolates sensor I/O lines during MCU sleep mode using OE-controlled 3-state output. Use Value: Reduces system standby current by disabling signal paths while preserving bus integrity and enabling wake-on-event. | Use Scenario: Interfacing door lock actuators and window motor drivers to a central BCM microcontroller. IC Role / Device Role / Timing Role: Buffers control signals between 3.3 V MCU and 5 V actuator drivers with precise timing control. Use Value: Ensures clean signal edge delivery (tdis ≤3.8 ns) and prevents latch-up during power sequencing faults. |
| Industrial PLC I/O Expansion | Wearable Health Monitor |
Use Scenario: Adding isolated digital inputs to modular PLC backplanes operating across mixed voltage rails. IC Role / Device Role / Timing Role: Provides voltage-level translation and bus contention protection between 2.5 V fieldbus and 3.3 V controller. Use Value: Eliminates need for discrete level shifters; IOFF prevents backfeed during module hot-swap maintenance. | Use Scenario: Managing ECG/PPG sensor data routing in compact wearable devices with strict size and power constraints. IC Role / Device Role / Timing Role: Enables low-latency sensor data multiplexing onto shared ADC interface with minimal board space. Use Value: XSON6 footprint (0.9 × 1.0 mm) saves >40% area vs. TSSOP5; ICC <1 μA extends battery runtime by weeks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G126DBVR | Higher ICC (max 10 μA), wider VCC (1.65–5.5 V), no IOFF or input-disable | Requires external pull-ups for floating inputs; unsuitable for true power-gated systems | Select when interfacing to 5 V peripherals and ultra-low ICC is not critical |
| 74LVC1G125GW,125 | Inverting function, identical package and VCC range, same IOFF and input-disable | Requires logic inversion in signal path; incompatible where polarity must be preserved | Choose only if system design accommodates inverted enable/control signals |
Compared with SN74LVC1G126DBVR and 74LVC1G125GW,125, the 74AUP1G126GN,132 delivers superior power efficiency (0.9 μA vs. 10 μA), built-in input-disable, and guaranteed IOFF behavior-making it optimal for battery-constrained, hot-swap-capable, and mixed-voltage embedded systems.
Availability
74AUP1G126GN,132 is available at Aetrix Electronics and suitable for portable sensor hubs, automotive body control modules, and industrial PLC I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G126GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
This device belongs to the 74AUP ultra-low-power logic family, engineered specifically for battery-powered and thermally constrained applications demanding sub-microamp quiescent current and robust noise immunity across wide supply ranges.
FAQ
What is the maximum capacitive load the 74AUP1G126GN,132 can drive while maintaining specified tpd?
The device is characterized up to 30 pF load capacitance. At VCC = 3.3 V and CL = 30 pF, propagation delay remains ≤5.8 ns (typical) and ≤8.3 ns (max over −40 °C to +125 °C). Driving loads beyond 30 pF increases delay nonlinearly and may degrade edge rate; external series termination is recommended for >50 pF.
Can the 74AUP1G126GN,132 safely interface between a 1.2 V MCU and a 3.3 V peripheral?
Yes. Its inputs accept voltages up to 3.6 V independent of VCC, and its outputs swing rail-to-rail (0 V to VCC). With VCC = 1.2 V, it drives 0–1.2 V outputs compatible with 1.2 V peripherals; with VCC = 3.3 V, it drives 0–3.3 V outputs. No level-shifting circuitry is needed for bidirectional voltage domain bridging.
Does the n.c. pin (Pin 5) require PCB routing or grounding?
No. Pin 5 is internally unconnected and must remain electrically floating on the PCB. Routing traces to or placing solder mask openings on this pad is unnecessary and may risk mechanical stress or contamination. The datasheet explicitly prohibits connection to any net, including GND or VCC.
How does the input-disable feature behave when OE is low and A is left unconnected?
When OE = LOW, the input stage of A is disabled, drawing ≤0.1 μA leakage current and presenting high impedance (>100 MΩ) to external circuits. This allows A to float without affecting device state or causing shoot-through, making it ideal for unused or dynamically configured I/O lines in reconfigurable systems.
74AUP1G126GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AUP1G126GN,132 FAQ
1.How can I place an order for 74AUP1G126GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G126GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G126GN,132 reliable?
The price and inventory of 74AUP1G126GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G126GN,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1G126GN,132?
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6.How does Aetrix verify that 74AUP1G126GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G126GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G126GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G126GN,132?
All 74AUP1G126GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G126GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G126GN,132 part is unused and in its original packaging.
Return procedure for 74AUP1G126GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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