Nexperia USA Inc. 74AUP1G126GS,132
- Part No.:
- 74AUP1G126GS,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G126GS,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
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Product details
Overview
74AUP1G126GS,132 from Nexperia is a single non-inverting 3-state buffer/line driver with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply. It features input-disable functionality, IOFF partial power-down protection, and ultra-low static current (≤0.9 μA max). Used in low-power I/O expansion, level translation, and bus isolation in portable and battery-powered systems.
For engineers reviewing the 74AUP1G126GS,132 datasheet, 74AUP1G126GS,132 pinout, 74AUP1G126GS,132 application, or 74AUP1G126GS,132 equivalent, key selection criteria include its 0.8–3.6 V wide-VCC operation, sub-1 μA ICC, 3-state enable timing (tdis ≤ 3.6 ns at 3.3 V), Schmitt-trigger noise immunity, and XSON6 (SOT1202) 1.0 × 1.0 × 0.35 mm package compatibility with high-density PCB layouts.
Technical Context
This device implements a single-channel non-inverting logic buffer with active-low 3-state output control (OE). Its Schmitt-trigger inputs tolerate slow-rising/falling signals across the full 0.8–3.6 V VCC range, enabling robust interfacing with noisy or RC-filtered sources. The input-disable feature deactivates inputs when OE is LOW, eliminating floating-input leakage and dynamic power.
The IOFF circuit ensures bidirectional isolation during partial power-down: when VCC = 0 V, backflow current is blocked even if A or Y are biased to 3.6 V. All pins tolerate up to 3.6 V regardless of VCC, supporting mixed-voltage system interfacing without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains. |
| Max Static Supply Current | 0.9 μA at VCC = 0.8–3.6 V - Ensures negligible battery drain in always-on standby modes. |
| Propagation Delay (A→Y) | 1.4–3.1 ns at VCC = 3.0–3.6 V, CL = 5 pF - Supports >300 MHz data rates in short-bus applications. |
| Enable/Disable Time | ten ≤ 2.9 ns, tdis ≤ 3.6 ns at VCC = 3.3 V - Minimizes bus contention windows during hot-swap or multiplexing. |
| Input Threshold Hysteresis | Typical 0.15 V at VCC = 1.2 V - Rejects noise spikes up to 150 mV on slow edges without external filtering. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - Prevents damaging back-current into powered-down subsystems. |
| ESD Robustness | HBM >5000 V, CDM >1000 V - Survives handling and board-level ESD events without shielding. |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT1202); no leads; 6 terminals; body dimensions 1.0 mm × 1.0 mm × 0.35 mm; thermal pad optional; RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable Input | Active-low control: LOW forces Y into high-impedance state and disables inputs (A floats safely). |
| 2 (A) | Data Input | Non-inverting input with Schmitt-trigger action; accepts 0–3.6 V regardless of VCC. |
| 3 (GND) | Ground Reference | 0 V reference for all voltage measurements and current return path. |
| 4 (Y) | Buffered Output | 3-state non-inverting output; drives loads up to ±20 mA; supports bus sharing. |
| 5 (n.c.) | No Connect | Internally unconnected terminal; must remain unconnected on PCB. |
| 6 (VCC) | Supply Voltage | Primary power rail; powers internal logic and output stage; decoupling capacitor required. |
Key Features
| Feature | Design Value |
|---|---|
| Wide-VCC Operation | 0.8–3.6 V enables single part to serve multiple voltage rails in heterogeneous SoC interfaces. |
| Input-Disable Function | OE LOW disables A input, eliminating leakage and dynamic switching current when output is tri-stated. |
| IOFF Partial Power-Down | Blocks >99.9% of backflow current when VCC = 0 V, protecting powered-down ICs in modular systems. |
| Schmitt-Trigger Inputs | Guarantees clean logic transitions on slow or noisy signals, removing need for external RC filters. |
| Ultra-Low ICC | 0.9 μA max ICC allows use in energy-harvesting and coin-cell-powered devices with multi-year battery life. |
Applications
| USB Peripheral Interface | IoT Sensor Node Bus Isolation |
|---|---|
Use Scenario: Isolating USB enumeration lines between host MCU and peripheral IC during sleep mode. IC Role / Device Role / Timing Role: 3-state buffer controlled by MCU GPIO to disconnect D+ line while preserving signal integrity. Use Value: Eliminates leakage paths that would prevent deep-sleep current <1 μA; Schmitt input rejects noise from shared PCB traces. | Use Scenario: Sharing I²C bus among multiple sensors with independent power domains. IC Role / Device Role / Timing Role: Bidirectional bus buffer enabling hot-plug sensor addition without bus contention. Use Value: IOFF protection prevents backfeed from powered sensors into unpowered MCU; 0.8 V min VCC supports ultra-low-voltage sensor operation. |
| Wearable Display Data Latch | Industrial PLC I/O Expansion |
Use Scenario: Driving segmented OLED display lines from a low-power microcontroller with variable VDD. IC Role / Device Role / Timing Role: Level-translating buffer ensuring clean 3.3 V output swing despite MCU running at 1.2 V. Use Value: Wide VCC range eliminates discrete level shifter; 1.4 ns propagation delay preserves timing margins in 20 MHz pixel clocks. | Use Scenario: Expanding digital input count on a 24 V PLC controller using 3.3 V FPGA I/O. IC Role / Device Role / Timing Role: Signal conditioner isolating FPGA from field-side transients via optocoupler-compatible input. Use Value: 5000 V HBM ESD rating withstands industrial EMI; n.c. pin simplifies layout in space-constrained DIN-rail modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G126DBVR | Higher ICC (10 μA typ), no IOFF, 1.65–5.5 V VCC range | Lacks partial power-down; requires external pull-downs for floating inputs | Select when higher drive strength (32 mA) and 5 V tolerance are needed over ultra-low power. |
| 74LVC1G125GW,125 | Inverting output, identical package and VCC range, same IOFF and Schmitt specs | Requires logic inversion in signal path; otherwise drop-in compatible | Choose only when system design mandates inverted enable or data polarity. |
Compared with SN74LVC1G126DBVR and 74LVC1G125GW,125, the 74AUP1G126GS,132 delivers superior static power efficiency (0.9 μA vs. 10 μA), native floating-input safety, and guaranteed IOFF protection-critical for battery longevity and modular power sequencing in modern embedded systems.
Availability
74AUP1G126GS,132 is available at Aetrix Electronics and suitable for USB peripheral interface, IoT sensor node bus isolation, wearable display data latching, and industrial PLC I/O expansion requiring stable component supply across automotive-grade temperature ranges (−40 °C to +125 °C).
Supply support for 74AUP1G126GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient components for automotive, industrial, mobile, and computing applications.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained systems requiring sub-microwatt static power, wide-VCC interoperability, and robust noise immunity-designed specifically for portable, wearable, and battery-operated electronics.
FAQ
What is the maximum load capacitance supported at 3.3 V without violating timing specs?
The datasheet guarantees tpd ≤ 3.8 ns and tdis ≤ 5.0 ns up to CL = 30 pF at VCC = 3.3 V and Tamb = 25 °C. At −40 °C to +125 °C, CL = 30 pF yields tpd ≤ 8.3 ns and tdis ≤ 12.0 ns-still within typical bus timing budgets for I²C, SPI, and GPIO expansion. Exceeding 30 pF increases propagation delay linearly and may require slew-rate limiting.
Can the 74AUP1G126GS,132 drive a 50 Ω transmission line directly?
No. Its output drive strength is rated for ±20 mA into resistive loads, not 50 Ω impedance matching. Driving a 50 Ω line would require ~66 mA at 3.3 V, exceeding absolute maximum ratings and causing signal distortion. Use a dedicated line driver (e.g., SN65LVDS1) for controlled-impedance signaling.
Does the n.c. pin (Pin 5) require PCB routing or grounding?
Pin 5 is internally unconnected and must remain unconnected on the PCB. No trace, pad, or thermal relief should be attached. Routing or grounding this pin risks mechanical stress on the die bond wire and violates Nexperia's SOT1202 assembly guidelines, potentially compromising long-term reliability.
How does the input-disable feature interact with Schmitt-trigger thresholds?
When OE is LOW, the input-disable circuit disconnects the A pin from internal logic, rendering Schmitt thresholds irrelevant-the input presents high impedance (>100 MΩ) and draws <0.1 μA. Schmitt behavior resumes only when OE returns HIGH, ensuring no false triggering during tri-state periods.
74AUP1G126GS,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT1202 (1x1)
74AUP1G126GS,132 FAQ
1.How can I place an order for 74AUP1G126GS,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G126GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G126GS,132 reliable?
The price and inventory of 74AUP1G126GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G126GS,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1G126GS,132?
For technical support, including 74AUP1G126GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G126GS,132 requirements.
6.How does Aetrix verify that 74AUP1G126GS,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G126GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G126GS,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G126GS,132?
All 74AUP1G126GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G126GS,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G126GS,132 part is unused and in its original packaging.
Return procedure for 74AUP1G126GS,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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