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Nexperia USA Inc. 74AUP1G126GW,125
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- Part No.:
- 74AUP1G126GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G126GW,125.pdf
- Description:
- IC BUF NON-INVERT 3.6V 5TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:75,218
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Product details
Overview
74AUP1G126GW,125 from Nexperia is a single non-inverting 3-state buffer/line driver in TSSOP5 (SOT353-1) package, operating from 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, input-disable functionality during OE low, and IOFF circuitry enabling partial power-down with <±0.75 μA off-state leakage. Used in voltage-level translation and bus isolation in ultra-low-power IoT sensor nodes.
For engineers reviewing the 74AUP1G126GW,125 datasheet, 74AUP1G126GW,125 pinout, 74AUP1G126GW,125 application, or 74AUP1G126GW,125 equivalent, key selection criteria include its 0.9 μA max ICC at 3.6 V, 1.4 ns min propagation delay at 3.3 V/CL=5 pF, -40 °C to +125 °C rating, and TSSOP5 thermal profile for space-constrained PCBs.
Technical Context
This device implements a single-channel non-inverting logic buffer with active-high output enable (OE), where OE LOW forces Y into high-impedance state and disables A input. Schmitt-trigger inputs ensure robust operation across full VCC range (0.8–3.6 V) with hysteresis ≥0.1 V typical, tolerating slow edges up to 200 ns/V.
The IOFF protection circuit actively blocks backflow current when VCC = 0 V, limiting IOFF to ±0.75 μA - critical for hot-swap and multi-rail systems. Input voltage tolerance extends to 3.6 V regardless of VCC, enabling mixed-voltage interfacing without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - supports direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC | 0.9 μA at VCC = 3.6 V - enables >10-year battery life in always-on sensor wake-up circuits |
| tpd (A→Y) | 1.4 ns min at VCC = 3.0 V, CL = 5 pF - meets timing closure for sub-500 MHz digital control loops |
| VIH / VIL | VIL ≤ 0.25×VCC, VIH ≥ 0.70×VCC at VCC = 0.8 V - ensures reliable switching with degraded signal integrity |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents cross-rail current in powered-down subsystems |
| Operating Temp | -40 °C to +125 °C - qualified for under-hood automotive and industrial motor drive control |
| ESD Rating | HBM >5000 V, CDM >1000 V - withstands handling and board assembly without additional protection |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, 0.8 mm height - optimized for automated placement and thermal dissipation in dense layouts.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE (Output Enable) | Active-HIGH control: HIGH enables non-inverting buffer; LOW disables output and input (floating-tolerant) |
| 2 | A (Data Input) | Schmitt-trigger input accepting 0–3.6 V; disabled when OE = LOW to prevent floating-induced current |
| 3 | GND | Reference ground terminal - must be low-inductance connection to minimize switching noise coupling |
| 4 | Y (Data Output) | 3-state non-inverting output; high-impedance when OE = LOW; drives up to ±4 mA at VCC = 3.0 V |
| 5 | VCC | Power supply input - decoupling capacitor (100 nF) required within 2 mm for stable high-speed operation |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC Range | 0.8 V to 3.6 V enables single-bom deployment across 0.9 V microcontrollers, 1.8 V FPGAs, and 3.3 V peripherals |
| Input-Disable Logic | Automatic A-input disable when OE = LOW eliminates static current from floating inputs in standby mode |
| IOFF Protection | Prevents damaging backflow current during partial power-down - essential for PCIe hot-plug and modular power systems |
| Schmitt-Trigger Inputs | ≥0.1 V hysteresis rejects noise on slow-rising signals (e.g., mechanical switch debouncing, long trace interfaces) |
| Low Dynamic Power | CPD = 4.2 pF at VCC = 3.3 V - reduces dynamic power by >60% vs. standard AUP series at same frequency |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating I²C/SPI lines between a 1.8 V MCU and 3.3 V analog sensor in a factory-floor vibration monitor. IC Role / Device Role / Timing Role: Level-shifting buffer with 3-state control synchronized to MCU sleep/wake cycles. Use Value: Eliminates external level translators; IOFF prevents sensor bias leakage during MCU deep-sleep (ICC < 1 μA). |
Use Scenario: Enabling/disabling CAN transceiver bias current during ignition-off state in door module ECU. IC Role / Device Role / Timing Role: Bus isolation gate controlled by microcontroller's power-management GPIO. Use Value: Reduces quiescent current by 2.3 μA per channel vs. standard buffer; -40 °C to +125 °C rating ensures reliability. |
| Wearable Health Monitor | Smart Home Hub Baseband |
|
Use Scenario: Driving low-capacitance electrode traces from an ultra-low-power 0.9 V ARM Cortex-M0+ core. IC Role / Device Role / Timing Role: Signal integrity-preserving buffer with Schmitt-trigger input rejecting EMI from nearby RF sections. Use Value: 20.6 ns tpd at 0.8 V allows real-time bio-signal sampling at 25 kHz without timing margin loss. |
Use Scenario: Isolating Zigbee/Thread radio baseband lines from host processor during firmware OTA updates. IC Role / Device Role / Timing Role: Controlled bus disconnect via OE to prevent radio lockup during host reset sequences. Use Value: 1.3 ns ten time ensures clean 3-state activation before host clock stops - avoids radio TX collision. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G126DBVR | Wider VCC (1.65–5.5 V); higher ICC (10 μA typ); no input-disable feature | Lacks IOFF and input-disable - unsuitable for partial power-down systems | Select only if 5 V compatibility is mandatory and system lacks hot-swap requirements |
| 74LVC1G125GW,125 | Inverting function; identical package, VCC range, and timing specs | Requires logic inversion in signal path - adds design complexity for non-inverting use cases | Choose only when inverting behavior aligns with existing schematic topology |
Compared with SN74LVC1G126DBVR and 74LVC1G125GW,125, the 74AUP1G126GW,125 uniquely delivers sub-μA static power, input-disable, and IOFF in a single non-inverting buffer - making it the only option for battery-critical, multi-rail, or hot-swap-sensitive designs.
Availability
74AUP1G126GW,125 is available at Aetrix Electronics and suitable for industrial sensor nodes, automotive body electronics, wearable health monitors, and smart home hubs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G126GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for automotive, industrial, and mobile markets.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications demanding nanowatt static power, wide VCC flexibility, and robust signal integrity - especially in battery-powered and thermally restricted environments.
FAQ
What is the maximum capacitive load the 74AUP1G126GW,125 can drive while maintaining specified tpd?
The device is characterized up to 30 pF load capacitance. At VCC = 3.3 V and CL = 30 pF, tpd is 4.6 ns (typical) and 5.8 ns (max) over -40 °C to +125 °C - verified per JEDEC JESD78 latch-up and JESD22-A114 HBM test standards. Exceeding 30 pF increases propagation delay nonlinearly and may violate setup/hold margins in synchronous systems.
Does the input-disable feature affect timing parameters like tpd or ten?
No - input-disable only gates internal input stage current when OE = LOW; it does not alter propagation or enable/disable timing. All dynamic specifications (tpd, ten, tdis) are measured with OE = HIGH and A switching. The feature solely reduces ICC by eliminating input leakage paths during standby.
Can 74AUP1G126GW,125 be used with VCC = 0.8 V and still meet VIH/VIL thresholds?
Yes - at VCC = 0.8 V, VIH is guaranteed ≥0.70 × VCC = 0.56 V and VIL ≤0.25 × VCC = 0.20 V. This provides 360 mV noise margin for 0.8 V logic systems, validated across -40 °C to +125 °C with Schmitt-trigger hysteresis ensuring monotonic transitions.
Is there a recommended PCB layout practice for minimizing ground bounce in high-frequency switching?
Place a 100 nF X7R ceramic decoupling capacitor between pins 3 (GND) and 5 (VCC), with trace length <2 mm and direct connection to solid ground plane. Avoid routing A or Y traces parallel to VCC/GND; maintain ≥3× trace width spacing to reduce crosstalk. Thermal pad (if present in variant) must be tied to GND with ≥4 thermal vias.
74AUP1G126GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G126GW,125 FAQ
1.How can I place an order for 74AUP1G126GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G126GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G126GW,125 reliable?
The price and inventory of 74AUP1G126GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G126GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G126GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G126GW,125 transactions.
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4.How is shipping managed for 74AUP1G126GW,125?
74AUP1G126GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G126GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G126GW,125?
For technical support, including 74AUP1G126GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G126GW,125 requirements.
6.How does Aetrix verify that 74AUP1G126GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G126GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G126GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G126GW,125?
All 74AUP1G126GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G126GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G126GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G126GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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