Nexperia USA Inc. 74AUP1G132GN,132

Overview

74AUP1G132GN,132 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in ultra-low-power systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and uses SOT1115 (XSON6) 6-terminal 0.9 × 1.0 × 0.35 mm package. It is used in wave shaping and multivibrator circuits where slow-edge tolerance and rail-to-rail input voltage compatibility are critical.

For engineers reviewing the 74AUP1G132GN,132 datasheet, 74AUP1G132GN,132 pinout, 74AUP1G132GN,132 application, or 74AUP1G132GN,132 equivalent, key selection criteria include Schmitt-trigger hysteresis (0.79–1.31 V at VCC = 3.0 V), propagation delay down to 1.4 ns (VCC = 3.0 V, CL = 5 pF), IOFF leakage ≤±0.75 μA at VCC = 0 V, overvoltage-tolerant inputs up to 3.6 V, and guaranteed operation from −40 °C to +125 °C.

Technical Context

This device implements a single NAND logic function with dual Schmitt-trigger inputs, enabling robust waveform regeneration from slow or noisy signals. Its hysteresis (VH) ranges from 0.07 V (VCC = 0.8 V) to 1.31 V (VCC = 3.0 V), and threshold voltages (VT+, VT−) shift proportionally with supply voltage-e.g., VT+ = 1.88–2.32 V and VT− = 0.88–1.24 V at VCC = 3.0 V.

The IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V, while maintaining input/output voltage tolerance up to 3.6 V regardless of supply state. Static power consumption remains ≤1.4 μA across full temperature and voltage range, and dynamic performance is characterized with CL = 5–30 pF loads and propagation delays specified per VCC band (e.g., 1.4–6.2 ns at VCC = 3.0–3.6 V).

Key Specifications

Pinout & Package

74AUP1G132GN,132 is housed in the SOT1115 (XSON6) package: an extremely thin, leadless 6-terminal outline measuring 0.9 × 1.0 × 0.35 mm, with terminal 1 index located on the lower-left corner below the marking code "aE".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NAND Schmitt-trigger applications.

Compared with 74LVC1G132GW,125 and SN74LVC1G132DBVR, the 74AUP1G132GN,132 uniquely supports 0.8 V operation, guarantees IOFF protection, and tolerates 3.6 V inputs at zero supply-making it the sole choice for energy-harvesting, battery-constrained, or mixed-voltage hot-swap designs.

Availability

74AUP1G132GN,132 is available at Aetrix Electronics and suitable for wave shapers, astable/monostable multivibrators, and power sequencing monitors requiring stable component supply across automotive, industrial, and portable electronics programs.

Supply support for 74AUP1G132GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications, delivering nanowatt static power and robust noise immunity without sacrificing speed or voltage flexibility.

FAQ

What is the minimum supply voltage for guaranteed operation?

The 74AUP1G132GN,132 is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, it maintains functional NAND behavior with VT+ = 0.30–0.62 V and VH = 0.07–0.50 V. Propagation delay increases to 22.5 ns (typical) at CL = 5 pF, but logic correctness and IOFF functionality remain guaranteed per datasheet Section 10.

How does the IOFF feature protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry disables the output driver, presenting a high-impedance state at Y. This prevents reverse current flow from powered downstream circuits (e.g., 3.3 V buses) into the unpowered IC, eliminating latch-up risk and meeting JEDEC JESD78 Class II latch-up requirements (>100 mA).

Can inputs exceed VCC without damage?

Yes - all inputs tolerate up to 3.6 V regardless of VCC level, including VCC = 0 V. This overvoltage capability is intrinsic to the input structure and does not require external clamping diodes, simplifying interface design with mixed-voltage subsystems.

Is the SOT1115 (XSON6) package compatible with standard reflow profiles?

Yes - the SOT1115 package (0.9 × 1.0 × 0.35 mm, 6-terminal, no leads) is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 and supports standard Pb-free reflow profiles (peak 260 °C). Its side-wettable flanks are not present in SOT1115 (unlike SOT8065-1), so optical solder inspection relies on X-ray or cross-section verification.