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Nexperia USA Inc. 74AUP1G132GS,132

Part No.:
74AUP1G132GS,132
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
-
Datasheet:
Aetrix74AUP1G132GS,132.pdf
Description:
IC 2-INP
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Inventory:150,000

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Product details

Overview

74AUP1G132GS,132 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in low-voltage digital systems. It operates across 0.8 V to 3.6 V supply, delivers <0.9 μA max ICC at 125 °C, features IOFF partial power-down protection, and uses XSON6 (SOT1202) 6-terminal package with 1.0 × 1.0 × 0.35 mm body. It enables robust wave shaping in battery-powered sensor interfaces.

For engineers reviewing the 74AUP1G132GS,132 datasheet, 74AUP1G132GS,132 pinout, 74AUP1G132GS,132 application, or 74AUP1G132GS,132 equivalent, key selection criteria include Schmitt-trigger hysteresis (0.79–1.31 V at 3.0 V), propagation delay as low as 1.4 ns (VCC = 3.0 V, CL = 5 pF), IOFF leakage ≤ ±0.75 μA at VCC = 0 V, input overvoltage tolerance to 3.6 V, and −40 °C to +125 °C operation.

Technical Context

This device implements a dual-threshold Schmitt-trigger input stage that converts slow-rising or noisy signals into clean logic transitions, with VT+ ranging from 0.30 V (VCC = 0.8 V) to 2.32 V (VCC = 3.0 V) and VT− from 0.10 V to 1.24 V. Its CMOS architecture ensures rail-to-rail output swing and sub-1 μA static current across full temperature range.

The IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V while inputs/outputs remain biased up to 3.6 V. Dynamic performance is load-dependent: tpd ranges from 1.4 ns (CL = 5 pF, VCC = 3.0 V) to 10.1 ns (CL = 30 pF, VCC = 3.0 V), with CPD fixed at 4.4 pF at 3.0–3.6 V.

Key Specifications

Parameter Value and Actual Design Meaning
Supply voltage 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters
ICC (max) 1.4 μA at −40 °C to +125 °C - enables multi-year battery life in always-on IoT edge nodes
IOFF leakage ±0.75 μA at VCC = 0 V - prevents cross-conduction in hot-swap or partial-power-down subsystems
VH (hysteresis) 0.79–1.31 V at VCC = 3.0 V - rejects >1.3 V peak noise without false triggering on analog-like inputs
tpd (min) 1.4 ns at VCC = 3.0 V, CL = 5 pF - sustains >500 MHz toggle rates in clocked feedback loops
Input overvoltage 3.6 V absolute max - allows safe connection to 3.3 V buses even when VCC = 0.8 V
ESD rating HBM >5000 V, CDM >1000 V - survives handling and board-level ESD events without shielding

Pinout & Package

XSON6 package (SOT1202): 6-terminal, leadless, 1.0 × 1.0 × 0.35 mm body with side-wettable flanks for automated optical inspection. Pin 1 indicator located at lower-left corner below marking code "aE".

Pin/Terminal Circuit Role Design Meaning
A Data input First Schmitt-trigger input; accepts slow edges (≥100 ns rise/fall) without oscillation
B Data input Second Schmitt-trigger input; electrically identical to A; both tolerate VI = 0–3.6 V
GND Ground reference 0 V return path for all internal logic and IOFF control; must be low-impedance
n.c. No connect Internally unconnected terminal; left floating per design - no external tie required
VCC Supply voltage Power rail for core logic and output drivers; IOFF activates automatically when VCC = 0 V
Y Data output NAND result (Y = NOT(A AND B)); drives CMOS loads up to 4 mA at 3.0 V with VOL ≤ 0.50 V

Key Features

Feature Design Value
Schmitt-trigger inputs VT+ and VT− thresholds provide ≥0.5 V hysteresis at 1.8 V supply, eliminating chatter on noisy sensor or switch inputs
IOFF partial power-down Output high-impedance state activated when VCC = 0 V, preventing backfeed current from live buses into powered-down sections
Overvoltage-tolerant I/O Inputs and outputs withstand 3.6 V regardless of VCC setting - enables mixed-supply system interoperability
Ultra-low ICC ≤1.4 μA max at 125 °C - reduces thermal load and extends runtime in energy-constrained wearables and remote sensors
JEDEC-compliant voltage ranges Fully specified across JESD8-12 (0.8–1.3 V), JESD8-11 (0.9–1.65 V), JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), and JESD8C (2.7–3.6 V)

Applications

Wave Shaping Astable Multivibrator

Use Scenario: Converting irregular analog pulses from photodiode or hall-effect sensors into clean square waves for microcontroller capture.

IC Role / Device Role / Timing Role: Signal conditioner and noise filter - transforms slow, noisy edges into monotonic logic transitions via hysteresis.

Use Value: Eliminates need for external RC filtering and comparator circuits, reducing BOM count and PCB area by ≥3 components.

Use Scenario: Generating precise clock signals in low-power timing circuits where crystal oscillators are impractical.

IC Role / Device Role / Timing Role: Core logic element in feedback loop with two external resistors and one capacitor to set oscillation frequency.

Use Value: Achieves stable 10 kHz–1 MHz oscillation with <5 % duty cycle variation across temperature, using only passive components.

Monostable Multivibrator Pushbutton Debounce

Use Scenario: Creating fixed-duration pulses from momentary switch closures in industrial HMI panels.

IC Role / Device Role / Timing Role: Triggered one-shot generator - initiates pulse on rising edge of input, duration set by RC network.

Use Value: Delivers 10–100 ms clean pulses with jitter <10 ns, replacing mechanical debounce hardware and firmware polling.

Use Scenario: Removing contact bounce from tactile switches in portable medical devices requiring zero false triggers.

IC Role / Device Role / Timing Role: Input synchronizer and metastability filter - Schmitt action suppresses sub-100 ns transients before MCU sampling.

Use Value: Guarantees single, deterministic edge per press across −40 °C to +125 °C, eliminating software debounce overhead.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND Schmitt trigger applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC1G132DBVR Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; SOT-23-5 package Requires ≥1.65 V supply; unsuitable for partial power-down systems; less ideal for sub-1 V battery operation Select when interfacing with 5 V logic or when IOFF is not required and board space permits larger SOT-23 footprint
74LVC1G132GW,125 Same AUP family but TSSOP5 (SOT353-1) package; identical electrical specs; 5-pin vs 6-pin layout Compatible functionally but requires PCB redesign due to different pin count, pad layout, and thermal profile Select only if legacy TSSOP5 assembly infrastructure exists and XSON6 reflow capability is unavailable

Compared with SN74LVC1G132DBVR, the 74AUP1G132GS,132 offers 10× lower ICC and IOFF support for power-gated systems; compared with 74LVC1G132GW,125, it provides superior thermal performance and smaller footprint but demands XSON6-compatible assembly.

Availability

74AUP1G132GS,132 is available at Aetrix Electronics and suitable for battery-powered sensor nodes, industrial pushbutton interfaces, wearable health monitors, and automotive body-control modules requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G132GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power digital signal conditioning in space- and energy-constrained applications such as IoT endpoints, portable diagnostics, and automotive sub-systems.

FAQ

What is the minimum supply voltage for guaranteed operation?

The 74AUP1G132GS,132 is fully specified from 0.8 V to 3.6 V per JEDEC standards JESD8-12 through JESD8C. At 0.8 V, it maintains functional Schmitt behavior with VT+ = 0.30–0.62 V and VH ≥ 0.07 V, enabling use in single-cell LiFePO₄ (nominal 3.2 V) or dual-cell NiMH (2.4 V) systems stepped down to 0.8 V.

Does the n.c. pin require grounding or pulling?

No. Pin 5 in the SOT1202 (XSON6) package is internally unconnected and must remain floating. Nexperia's datasheet explicitly states "n.c." with no recommended external bias; connecting it risks unintended coupling or solder bridging in fine-pitch assembly.

How does IOFF behave when VCC is ramping?

IOFF activates when VCC falls below ~0.2 V and remains active until VCC rises above ~0.4 V. During this transition, output leakage is limited to ±0.75 μA maximum, preventing bus contention in systems where multiple supplies sequence independently - confirmed by ΔIOFF test data in Table 7.

Can this device drive a 50 pF load reliably?

While not characterized beyond 30 pF in the datasheet, the 74AUP1G132GS,132 can drive 50 pF with measurable degradation: tpd increases to ~12 ns at VCC = 3.0 V (extrapolated from 30 pF data), and VOH drops to ~2.25 V at IO = −4 mA. For production designs, limit CL to ≤30 pF unless validated under worst-case voltage/temperature conditions.

74AUP1G132GS,132 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
*
Package/Case:
-
Packaging:
Bulk
Product Status:
Active
Logic Type:
-
Number of Circuits:
-
Number of Inputs:
-
Features:
-
Voltage - Supply:
-
Current - Quiescent (Max):
-
Current - Output High, Low:
-
Input Logic Level - Low:
-
Input Logic Level - High:
-
Max Propagation Delay @ V, Max CL:
-
Operating Temperature:
-
Grade:
-
Qualification:
-
Mounting Type:
-
Supplier Device Package:
-

74AUP1G132GS,132 FAQ

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The price and inventory of 74AUP1G132GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G132GS,132 is usually 5 days.

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5.How can I obtain technical support or documentation for 74AUP1G132GS,132?

For technical support, including 74AUP1G132GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G132GS,132 requirements.

6.How does Aetrix verify that 74AUP1G132GS,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G132GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G132GS,132 meets industry standards.

7.What is the process for return or replacement of 74AUP1G132GS,132?

All 74AUP1G132GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G132GS,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G132GS,132 part is unused and in its original packaging.

Return procedure for 74AUP1G132GS,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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