Nexperia USA Inc. 74AUP1G132GW,125

Overview

74AUP1G132GW,125 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in low-voltage digital systems. It operates across 0.8 V to 3.6 V supply, delivers <0.9 μA max ICC at 25 °C, features IOFF partial power-down protection, and supports –40 °C to +125 °C ambient operation in TSSOP5 (SOT353-1) package. It is used in wave shaping and multivibrator circuits where input signal integrity is compromised by slow edges.

For engineers reviewing the 74AUP1G132GW,125 datasheet, 74AUP1G132GW,125 pinout, 74AUP1G132GW,125 application, or 74AUP1G132GW,125 equivalent, key selection criteria include Schmitt-trigger hysteresis voltage (0.79–1.31 V at VCC = 3.0 V), propagation delay (1.4–6.2 ns over VCC and load), IOFF leakage (<±0.75 μA at VCC = 0 V), overvoltage-tolerant inputs (to 3.6 V), and thermal-enhanced operation up to +125 °C.

Technical Context

The device implements a dual-threshold Schmitt-trigger input stage (VT+ and VT−) enabling robust noise rejection on slow-rising/falling signals-critical for debouncing mechanical switches or recovering degraded clock edges. Its AUP (Advanced Ultra-low Power) CMOS process ensures sub-1 μA static current while maintaining rail-to-rail output swing and fast propagation (as low as 1.4 ns at VCC = 3.0 V, CL = 5 pF).

IOFF circuitry actively disables outputs during power-down, blocking backflow current when VCC = 0 V-essential for hot-swap and multi-rail system interoperability. Input tolerance to 3.6 V independent of VCC allows interfacing with higher-voltage logic domains without level shifters.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad optional. Pin 1 index located below marking code at lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NAND Schmitt trigger applications.

Compared with SN74LVC1G132DBVR and 74LVC1G132GW,125, the 74AUP1G132GW,125 uniquely supports 0.8 V operation, delivers sub-1 μA static current, and includes IOFF-making it the only option for battery-powered, multi-rail, or hot-swap-capable systems requiring Schmitt-trigger NAND functionality.

Availability

74AUP1G132GW,125 is available at Aetrix Electronics and suitable for wave shapers, astable/monostable multivibrators, switch debouncers, and low-voltage logic interface circuits requiring stable component supply across industrial, automotive, and portable electronics programs.

Supply support for 74AUP1G132GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP1G132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family-engineered specifically for battery-constrained and multi-voltage embedded systems demanding nanowatt static power and robust signal integrity.

FAQ

What is the minimum supply voltage at which 74AUP1G132GW,125 guarantees full functionality?

The device is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, it maintains guaranteed VOH/VOL levels (VCC − 0.1 V and 0.1 V respectively), propagation delay ≤22.5 ns (CL = 5 pF), and hysteresis ≥0.07 V-enabling operation in energy-harvesting and coin-cell-powered systems.

How does the IOFF feature behave during system power sequencing?

When VCC drops to 0 V, the IOFF circuit automatically disables the output driver, limiting Y-terminal leakage to ±0.75 μA. This prevents reverse current flow from powered downstream logic into the unpowered IC-critical for safe power sequencing in multi-rail FPGAs or processors with staggered supply ramps.

Can 74AUP1G132GW,125 interface directly with 3.3 V inputs while operating at 1.2 V VCC?

Yes. Inputs tolerate up to 3.6 V regardless of VCC level. With VCC = 1.2 V, VIH is ~0.72 V (0.6 × VCC) and VIL is ~0.36 V (0.3 × VCC), so a 3.3 V logic HIGH safely exceeds VIH, and the overvoltage rating protects internal structures-no external clamping required.

What is the practical impact of Schmitt-trigger hysteresis on signal integrity?

Hysteresis (0.79–1.31 V at VCC = 3.0 V) creates distinct VT+ and VT− thresholds, eliminating multiple toggles caused by noise or slow edges. For example, a 100 mV peak-to-peak noise riding on a 2.5 V signal will not cause false triggering-only crossings beyond VT+ or VT− produce output transitions.