Nexperia USA Inc. 74AUP1G132GW-Q100H

Overview

74AUP1G132GW-Q100 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in automotive powertrain and body control modules. It operates across 0.8 V to 3.6 V supply, delivers <0.9 μA max ICC at 125 °C, features IOFF for partial power-down, and is AEC-Q100 Grade 1 qualified (−40 °C to +125 °C).

For engineers reviewing the 74AUP1G132GW-Q100 datasheet, 74AUP1G132GW-Q100 pinout, 74AUP1G132GW-Q100 application, or 74AUP1G132GW-Q100 equivalent, this device is selected for robust edge detection in low-voltage sensor interfaces, wave shaping in LIN bus subsystems, and monostable timing in automotive lighting controllers where input rise/fall time tolerance and ultra-low static power are critical.

Technical Context

The device implements a dual-threshold Schmitt-trigger input stage (VT+ = 0.88–2.32 V, VT− = 0.10–1.24 V at VCC = 0.8–3.0 V) enabling reliable hysteresis-based noise rejection on slow-rising signals. Its CMOS architecture supports rail-to-rail output swing and overvoltage-tolerant inputs up to 3.6 V independent of VCC.

IOFF circuitry actively disables outputs during power-down (VCC = 0 V), limiting backflow current to ±0.75 μA, while latch-up immunity exceeds 100 mA per JESD78 Class II. Propagation delay ranges from 1.4 ns (VCC = 3.0 V, CL = 5 pF) to 27.9 ns (VCC = 1.1 V, CL = 15 pF), scaling predictably with load and supply voltage.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, 1.1 × 2.2 × 1.0 mm footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input Schmitt-trigger NAND gate applications.

Compared with SN74LVC1G132DRYR and 74LVC1G132GV,125, the 74AUP1G132GW-Q100 uniquely combines Grade 1 qualification, sub-1 μA ICC, and IOFF - making it the sole choice for safety-critical, always-on automotive nodes requiring zero-power-state integrity.

Availability

74AUP1G132GW-Q100 is available at Aetrix Electronics and suitable for automotive powertrain control units, body electronics modules, and ADAS sensor interface circuits requiring stable component supply under extended temperature and long lifecycle commitments.

Supply support for 74AUP1G132GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.

This device belongs to the AUP (Advanced Ultra-low Power) logic family, engineered specifically for automotive-grade signal integrity and energy efficiency in battery-sensitive and thermally constrained electronic control units.

FAQ

What is the maximum input voltage the 74AUP1G132GW-Q100 can tolerate when VCC = 0.8 V?

The device accepts input voltages up to 3.6 V regardless of VCC level, as confirmed in Section 7.2 (Pin Description) and Table 5 (Limiting Values). This overvoltage tolerance allows direct connection to higher-voltage buses without level shifters or clamping diodes, simplifying interface design in mixed-supply automotive systems.

How does the IOFF feature behave during system power-down sequences?

When VCC drops to 0 V, the IOFF circuitry disables the output (Pin 4), limiting leakage current to ±0.75 μA (Table 7, Tamb = −40 °C to +125 °C). This prevents back-current flow from powered downstream circuits into the unpowered gate, protecting both the IC and connected devices during hot-swap or partial shutdown events.

Can this device replace standard 74AUP1G00 logic in existing designs?

No - the 74AUP1G132GW-Q100 has Schmitt-trigger inputs, unlike the standard 74AUP1G00's CMOS inputs. Its VT+ and VT− thresholds (e.g., 0.88–2.32 V and 0.10–1.24 V at VCC = 3.0 V) provide hysteresis for noise rejection, whereas the 74AUP1G00 lacks input hysteresis and is susceptible to chatter on slow or noisy signals.

What is the minimum propagation delay achievable with this device?

The shortest guaranteed propagation delay is 1.4 ns (typical 2.9 ns) at VCC = 3.0 V with CL = 5 pF, per Table 9. This occurs under optimal conditions: 25 °C ambient, nominal VCC, and minimal capacitive loading - enabling use in high-speed pulse shaping for LIN diagnostics and sensor wake-up timing.