Nexperia USA Inc. 74AUP1G14GVH

Overview

74AUP1G14GV from Nexperia is a single low-power Schmitt-trigger inverter IC designed for signal conditioning in ultra-low-voltage digital systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and provides hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V) for noise-immune waveform shaping in battery-powered sensor interfaces.

For engineers reviewing the 74AUP1G14GV datasheet, 74AUP1G14GV pinout, 74AUP1G14GV application, or 74AUP1G14GV equivalent, this device is selected for robust edge detection in mixed-voltage I/O domains, low-quiescent-power timing circuits, and rail-to-rail input-tolerant signal inversion where static current <1.5 μA and propagation delay ≤4.0 ns (VCC = 3.0 V, CL = 5 pF) are critical.

Technical Context

The 74AUP1G14GV implements a CMOS-based Schmitt-trigger input stage with asymmetric threshold voltages (VT+ = 1.88–2.32 V, VT− = 0.88–1.24 V at VCC = 3.0 V), enabling reliable noise rejection on slow-rising signals. Its IOFF circuit actively disables outputs during VCC = 0 V, blocking backflow current and supporting hot-swap and partial power-down architectures.

It supports JEDEC-compliant voltage ranges (JESD8-12 through JESD8C), exhibits ≤0.75 μA input leakage (VI = GND to 3.6 V), and maintains stable VOH/VOL performance across −40 °C to +125 °C - verified per Table 7 static characteristics under full temperature and supply sweep conditions.

Key Specifications

Pinout & Package

74AUP1G14GV uses the SC-74A (SOT753) surface-mount package: plastic, 5-lead, body size 3.0 × 1.7 × 0.9 mm, with gull-wing leads and pin 1 indicator below marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Schmitt-trigger inverter applications.

Compared with SN74LVC1G14DBVR and 74LVC1G14GW,125, the 74AUP1G14GV offers unique sub-1 V operation, lowest ICC (<1.5 μA), and mandatory IOFF - making it the sole choice for energy-constrained, multi-rail, or ultra-low-voltage designs where leakage and supply flexibility are non-negotiable.

Availability

74AUP1G14GV is available at Aetrix Electronics and suitable for battery-powered sensors, portable medical devices, and automotive body electronics requiring stable component supply across extended temperature ranges (−40 °C to +125 °C) and long product lifecycles.

Supply support for 74AUP1G14GV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP1G14GV belongs to the Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-critical and thermally constrained applications where nanowatt static consumption and robust noise immunity outweigh raw speed requirements.

FAQ

What is the minimum supply voltage for guaranteed operation of the 74AUP1G14GV?

The 74AUP1G14GV is fully specified from 0.8 V to 3.6 V per Table 6. At 0.8 V, propagation delay increases to 19.9 ns (CL = 5 pF), and VOH drops to VCC − 0.1 V, but all logic functions, hysteresis, and IOFF remain operational - confirmed across −40 °C to +125 °C per datasheet Section 10.

Does the 74AUP1G14GV require external pull-up or pull-down resistors on its inputs?

No. The Schmitt-trigger input has defined VT+ and VT− thresholds across all VCC values (e.g., 1.88 V / 0.88 V at 3.0 V), eliminating floating-input risk. Internal input structure ensures stable logic states without external biasing - verified by II ≤ ±0.75 μA and no requirement for external termination in Sections 7.2 and 11.

Can the 74AUP1G14GV drive a 50 pF load reliably?

While not characterized beyond 30 pF in the datasheet, the output stage delivers ±4 mA drive strength (Table 7). At VCC = 3.0 V, tpd increases ~2× from 4.0 ns (5 pF) to ~7.4 ns (30 pF); extrapolating linearly suggests ~10 ns at 50 pF - still functional for <100 MHz applications. Layout best practices (short traces, ground plane) are recommended.

How does the IOFF feature behave when VCC is ramping from 0 V to nominal?

IOFF activates automatically when VCC falls below ~0.2 V (ΔIOFF spec), disabling the output driver and limiting VI/VO leakage to ±0.75 μA. During power-up, the output remains high-impedance until VCC exceeds ~0.5 V, then transitions to normal operation - ensuring no contention during brown-out or sequencing events as validated in Section 2 and Table 7.