Nexperia USA Inc. 74AUP1G17GM,115

Overview

74AUP1G17GM,115 from Nexperia is a single-channel CMOS Schmitt-trigger buffer optimized for ultra-low-power operation across 0.8 V to 3.6 V supply rails. It provides hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V), IOFF-enabled partial power-down protection, and guaranteed operation from −40 °C to +125 °C - deployed in battery-powered sensor interfaces and noise-prone industrial I/O conditioning.

For engineers reviewing the 74AUP1G17GM,115 datasheet, 74AUP1G17GM,115 pinout, 74AUP1G17GM,115 application, or 74AUP1G17GM,115 equivalent, key selection criteria include input hysteresis voltage, IOFF leakage (< ±0.75 μA at VCC = 0 V), propagation delay (1.5–4.0 ns at CL = 5 pF, VCC = 3.0 V), static ICC (≤1.4 μA), and XSON6 package thermal performance (SOT886, 1.0 × 1.45 × 0.5 mm).

Technical Context

This device implements a single non-inverting Schmitt-trigger buffer with asymmetric input thresholds (VT+ = 1.88–2.32 V, VT− = 0.88–1.24 V at VCC = 3.0 V) to reject slow-rising or noisy signals. Its IOFF circuit actively disables output terminals during power-down, blocking backflow current when VCC = 0 V.

Designed for mixed-voltage systems, it complies with JEDEC standards JESD8-12 through JESD8C and supports overvoltage-tolerant inputs up to 3.6 V independent of VCC. ESD robustness meets HBM >5000 V and CDM >1000 V per JS-001/JS-002.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flank terminations for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Schmitt-trigger buffer applications.

Compared with SN74LVC1G17DBVR and 74LVC1G17GW,125, the 74AUP1G17GM,115 delivers superior ultra-low-power operation below 1.2 V, IOFF-enabled system-level power management, and smallest-footprint XSON6 packaging - making it optimal for energy-sensitive, thermally constrained, and mixed-voltage embedded designs.

Availability

74AUP1G17GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, wearable health monitors, and IoT edge nodes requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G17GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and thermally constrained applications, emphasizing sub-μA static current, wide VCC scalability, and robust IOFF functionality for modern embedded systems.

FAQ

What is the maximum input voltage the 74AUP1G17GM,115 can tolerate when VCC = 1.2 V?

The device supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC level. When VCC = 1.2 V, VI may safely reach 3.6 V without damage or functional disruption - enabling direct interface to higher-voltage peripherals without external clamping diodes or level shifters.

Does the 74AUP1G17GM,115 require external pull-up or pull-down resistors on its input or output?

No. The Schmitt-trigger input has defined threshold voltages (VT+, VT−) and does not float; the CMOS output has rail-to-rail drive capability. External resistors are unnecessary unless specific bus-termination or fail-safe biasing is required by system architecture - not inherent to device operation.

How does the IOFF feature behave during power sequencing when VCC ramps from 0 V to 3.3 V?

IOFF activates automatically when VCC drops below ~0.2 V, disabling the output and limiting leakage to ±0.75 μA. During ramp-up, the output remains in high-impedance state until VCC exceeds the minimum functional threshold (~0.8 V), then transitions to normal operation - preventing glitch generation or contention on shared buses.

Can the 74AUP1G17GM,115 drive a 50 pF capacitive load reliably at 10 MHz?

At CL = 50 pF and f = 10 MHz, dynamic power dissipation rises significantly due to CPD = 4.0 pF and load-driven switching. While functional, propagation delay increases to ~7.5 ns (extrapolated from CL = 30 pF data), and total power may exceed 100 μW. For such loads, verify thermal margin and signal integrity via IBIS simulation or bench validation.