Nexperia USA Inc. 74AUP1G17GW,125
- Part No.:
- 74AUP1G17GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G17GW,125.pdf
- Description:
- IC BUF NON-INVERT 3.6V 5TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,652
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP1G17GW,125 from Nexperia is a single-channel Schmitt-trigger buffer IC designed for noise-immune signal conditioning in ultra-low-power systems. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, features IOFF circuitry for partial power-down protection, and supports −40 °C to +125 °C industrial/automotive environments.
For engineers reviewing the 74AUP1G17GW,125 datasheet, 74AUP1G17GW,125 pinout, 74AUP1G17GW,125 application, or 74AUP1G17GW,125 equivalent, this device is selected for robust input hysteresis (e.g., ≥0.79 V at 3.0 V), rail-to-rail output swing, low dynamic power (CPD = 4.0 pF), and compatibility with mixed-voltage I/O domains in battery-powered sensors and interface level-shifting circuits.
Technical Context
The 74AUP1G17GW implements a CMOS-based Schmitt-trigger input stage with asymmetric positive-going (VT+) and negative-going (VT−) thresholds-e.g., VT+ = 1.88–2.32 V and VT− = 0.88–1.24 V at VCC = 3.0 V-to reject slow-rising or noisy signals. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current.
It uses a single-stage buffered output with propagation delay as low as 1.5 ns (CL = 5 pF, VCC = 3.0 V) and exhibits <10 % overshoot/undershoot. Input clamping and ESD protection (HBM >5000 V, CDM >1000 V) ensure reliability in harsh PCB environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Max ICC (125 °C) | 0.9 μA - ensures sub-1 μA static power draw in always-on sensor nodes or real-time clock buffers |
| Hysteresis (VH) | 0.79–1.31 V at VCC = 3.0 V - provides ≥26 % of supply voltage margin for reliable noise rejection on slow analog-like inputs |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents cross-talk and bus contention when upstream logic is powered down |
| Propagation Delay | 1.5 ns (min) at VCC = 3.0 V, CL = 5 pF - supports >200 MHz signal edge rates in timing-critical debounce or clock clean-up paths |
| ESD Rating | HBM >5000 V, CDM >1000 V - meets IEC 61000-4-2 Level 4 system-level ESD immunity requirements |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive, industrial motor control, and outdoor IoT deployments |
Pinout & Package
TSSOP5 (SOT353-1) package: 5-lead plastic thin shrink small outline, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No internal connection - must be left floating or grounded per board layout best practices; no electrical function |
| 2 | A | Schmitt-trigger input - accepts 0–3.6 V overvoltage-tolerant signals regardless of VCC level |
| 3 | GND | Ground reference - shared return path for supply and signal; requires low-impedance PCB plane |
| 4 | Y | Push-pull CMOS output - drives high/low to full VCC/GND rails with ±4 mA drive strength at 3.0 V |
| 5 | VCC | Power supply - decoupling capacitor (100 nF) required within 3 mm of pin for stable operation |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8–3.6 V operation eliminates need for external regulators in multi-rail portable systems |
| IOFF circuitry | Enables safe hot-insertion and partial power-down in modular subsystems without latch-up risk |
| High noise immunity | Input hysteresis ≥0.79 V at 3.0 V suppresses EMI-induced false triggering on long traces or unshielded cables |
| Low dynamic power | CPD = 4.0 pF enables <1 μW dynamic dissipation at 1 MHz, critical for energy harvesting applications |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC - simplifies interfacing with higher-voltage legacy peripherals |
Applications
| Industrial Sensor Interface | Automotive Body Control |
|---|---|
Use Scenario: Conditioning slow-rising analog switch signals from door latch or seat position sensors before MCU GPIO sampling. IC Role / Device Role / Timing Role: Schmitt-trigger buffer providing hysteresis-based noise filtering and level translation to MCU-compatible logic levels. Use Value: Eliminates software debouncing overhead and prevents spurious wake-ups due to contact bounce or EMI. | Use Scenario: Cleaning PWM signals from body control module (BCM) microcontrollers driving LED interior lighting. IC Role / Device Role / Timing Role: Signal integrity conditioner ensuring clean, rail-to-rail edges despite trace inductance and capacitive loading. Use Value: Reduces LED flicker and extends driver MOSFET lifetime by minimizing switching losses from distorted edges. |
| Portable Medical Wearable | Smart Home Hub Interface |
Use Scenario: Buffering low-power biopotential electrode signals into an ultra-low-power ADC front-end. IC Role / Device Role / Timing Role: Low-ICC signal conditioner preserving battery life while rejecting 50/60 Hz mains interference via hysteresis. Use Value: Enables >1-year coin-cell operation without compromising signal fidelity or noise margin. | Use Scenario: Interfacing 3.3 V Wi-Fi SoC GPIOs with 1.8 V touch controller or display driver in compact hub PCBs. IC Role / Device Role / Timing Role: Bidirectional voltage-domain translator leveraging overvoltage-tolerant inputs and rail-swing outputs. Use Value: Avoids dedicated level-shifters, saving BOM cost and board area in space-constrained consumer designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G17DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; HBM = 2000 V | Not suitable for sub-1.65 V operation or partial power-down systems | Select when interfacing with 5 V peripherals and IOFF is unnecessary |
| 74LVC1G17GW,125 | Same TSSOP5 package; VCC = 1.65–5.5 V; ICC = 10 μA max; no IOFF; lower hysteresis (≈0.3 V at 3.3 V) | Lacks robustness for battery-backed or mixed-voltage hot-swap use cases | Prefer only if legacy LVC family compatibility is mandatory and 0.8 V operation is not required |
Compared with SN74LVC1G17DBVR and 74LVC1G17GW,125, the 74AUP1G17GW,125 uniquely supports 0.8 V operation, achieves sub-1 μA static current, and includes IOFF-making it the sole choice for energy-sensitive, multi-rail, or hot-pluggable embedded systems.
Availability
74AUP1G17GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, portable medical wearables, and smart home hub designs requiring stable component supply across extended temperature and ultra-low-power constraints.
Supply support for 74AUP1G17GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable, and scalable logic, discrete, and MOSFET solutions.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-constrained applications where nanowatt static power, wide supply flexibility, and robust signal integrity are mandatory design requirements.
FAQ
What is the minimum supply voltage for guaranteed operation of the 74AUP1G17GW,125?
The 74AUP1G17GW,125 is fully specified from 0.8 V to 3.6 V. At 0.8 V, it maintains functional Schmitt-trigger behavior with VIH/VIL thresholds defined and propagation delay characterized (19.0 ns typical, CL = 5 pF). Below 0.8 V, performance is not guaranteed per datasheet limits.
Does the 74AUP1G17GW,125 require external pull-up or pull-down resistors on its input or output?
No. The device has no internal pull resistors, but its Schmitt-trigger input provides inherent noise immunity without external components. The push-pull output drives actively high/low-no pull-up is needed unless open-drain emulation is required, which is not supported by this part's architecture.
Can the 74AUP1G17GW,125 safely interface between a 3.3 V microcontroller and a 1.2 V FPGA I/O bank?
Yes-the input is overvoltage tolerant to 3.6 V independent of VCC, so a 3.3 V MCU output can directly drive pin A even when VCC = 1.2 V. The output swings rail-to-rail (0 V to 1.2 V), making it compatible with 1.2 V FPGA inputs meeting VIH ≥ 0.65 V and VIL ≤ 0.35 V.
How does the IOFF feature behave when VCC is ramping during power-up or power-down sequences?
IOFF activates when VCC falls below ~0.2 V, disabling the output to prevent backflow current. During power-up, the output remains in high-impedance until VCC exceeds the minimum functional threshold (~0.6 V), ensuring glitch-free startup. This behavior is verified per JESD78 latch-up testing and documented in Section 2 of the datasheet.
74AUP1G17GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G17GW,125 FAQ
1.How can I place an order for 74AUP1G17GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G17GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G17GW,125 reliable?
The price and inventory of 74AUP1G17GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G17GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G17GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G17GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G17GW,125?
74AUP1G17GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G17GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G17GW,125?
For technical support, including 74AUP1G17GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G17GW,125 requirements.
6.How does Aetrix verify that 74AUP1G17GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G17GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G17GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G17GW,125?
All 74AUP1G17GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G17GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G17GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G17GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G17GW,125 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

.jpg)