Nexperia USA Inc. 74AUP1G19GS,132

Overview

74AUP1G19GS,132 from Nexperia is a low-power 1-of-2 decoder/demultiplexer with active-low enable (E), true (1Y) and complement (2Y) outputs, Schmitt-trigger inputs, IOFF partial power-down support, and operation across 0.8 V to 3.6 V supply. It buffers input A to both outputs when E is LOW and forces both outputs HIGH when E is HIGH-used in voltage-level-flexible signal routing for portable sensors and battery-powered microcontroller I/O expansion.

For engineers reviewing the 74AUP1G19GS,132 datasheet, 74AUP1G19GS,132 pinout, 74AUP1G19GS,132 application, or 74AUP1G19GS,132 equivalent, key selection factors include its ultra-low ICC (≤1.4 µA at +125 °C), IOFF leakage (±0.75 µA at VCC = 0 V), 6-terminal XSON6 package (SOT1202), Schmitt-trigger noise immunity, and guaranteed operation from –40 °C to +125 °C.

Technical Context

This device implements a single-input, dual-output decoding function with asynchronous enable control. Its Schmitt-trigger inputs tolerate slow-rising/falling signals up to 200 ns/V transition rate, and the IOFF circuit actively disables outputs during power-down to prevent backflow current when VCC = 0 V.

The logic behavior is strictly defined by its truth table: E = L enables pass-through of A to 1Y (true) and 2Y (complement); E = H forces both outputs high regardless of A. Propagation delay ranges from 1.0 ns (VCC = 3.3 V, CL = 5 pF) to 3.9 ns (–40 °C to +125 °C, same conditions), ensuring timing predictability in mixed-voltage systems.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (no leads); 6 terminals; body dimensions 1.0 mm × 1.0 mm × 0.35 mm (SOT1202). Pin 1 indicator located on lower left corner below marking code "pY".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 1-of-2 decoder/demultiplexer applications.

Compared with SN74LVC1G19DBVR and 74LVC1G19GW,125, the 74AUP1G19GS,132 uniquely delivers sub-µA static current, certified IOFF protection, and the smallest XSON6 footprint-making it optimal for battery-critical, multi-voltage, and miniaturized designs.

Availability

74AUP1G19GS,132 is available at Aetrix Electronics and suitable for portable sensor hubs, low-power MCU I/O expansion, automotive body control modules, and USB-C power delivery sequencing requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G19GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor expert in high-volume, high-reliability logic, analog, and MOSFET solutions, headquartered in Nijmegen, Netherlands, serving automotive, industrial, and consumer markets globally.

The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications demanding nanowatt static power, wide VCC scalability, and robust IOFF protection-designed specifically for battery-powered and thermally sensitive systems.

FAQ

Can 74AUP1G19GS,132 operate with VCC = 0.8 V while driving a 3.3 V-tolerant load?

Yes. Its overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC, and outputs swing rail-to-rail (VOH ≈ VCC, VOL < 0.1 V) at 0.8 V. The load must interpret 0.8 V as valid HIGH and 0 V as valid LOW per its own input thresholds-verified for 3.3 V CMOS loads with VIH > 2.0 V and VIL < 0.9 V.

What happens to outputs 1Y and 2Y when VCC is removed but A and E remain at 3.3 V?

With VCC = 0 V, the IOFF circuit activates, disabling both outputs. Measured IOFF leakage is ±0.75 µA maximum-preventing harmful back-current into the unpowered device. Neither 1Y nor 2Y sources or sinks significant current, preserving system integrity during partial power-down.

Is the propagation delay matched between 1Y and 2Y outputs?

Yes. Per datasheet Table 8, tPLH and tPHL are identical for A→1Y and A→2Y paths under identical test conditions (CL, VCC, temperature). Skew is specified as ≤0.3 ns across all operating ranges, enabling use in synchronous dual-output applications like complementary clock gating.

Does the Schmitt-trigger input eliminate the need for external RC filtering on noisy switch inputs?

Yes. With typical hysteresis >0.3×VCC (e.g., ~0.9 V at 3.0 V VCC), the Schmitt action rejects noise spikes <1.5× the hysteresis window. This allows direct connection of mechanical switches or long cables without external debounce components-reducing BOM cost and board area.