NXP Semiconductors 74AUP1G240GF,132
- Part No.:
- 74AUP1G240GF,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G240GF,132.pdf
- Description:
- IC BUFFER INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:102,692
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Product details
Overview
74AUP1G240GF,132 from Nexperia is a single-bit low-power inverting buffer/line driver with 3-state output and Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering 2.3 ns propagation delay at 3.0 V, 5 pF load, and 0.9 μA max ICC, used for noise-immune signal conditioning in battery-powered IoT sensor interfaces.
For engineers reviewing the 74AUP1G240GF,132 datasheet, 74AUP1G240GF,132 pinout, 74AUP1G240GF,132 application, or 74AUP1G240GF,132 equivalent, key selection criteria include its IOFF-enabled partial power-down capability, ±0.75 μA max input leakage over –40 °C to +125 °C, and 0.36 V VOL at 3.0 V/2.7 mA drive - critical for interfacing with ultra-low-voltage MCUs and mixed-supply systems.
Technical Context
This device implements a single inverting logic gate with active-low 3-state control via OE, where HIGH on OE forces Y into high-impedance mode. Its Schmitt-trigger inputs tolerate slow-rising signals (Δt/ΔV ≤ 200 ns/V), enabling robust operation with RC-debounced switches or noisy analog-sensor outputs.
The IOFF circuit actively disables outputs during VCC = 0 V, limiting backflow current to ±0.75 μA, while overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC - supporting level-shifting between 1.2 V, 1.8 V, and 3.3 V domains without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interface with sub-1 V logic cores and legacy 3.3 V peripherals |
| Max ICC (Static) | 1.4 μA at –40 °C to +125 °C - ensures <1 μW static power at 1.2 V, ideal for always-on wake-up circuits |
| tpd (A→Y) | 2.3 ns at VCC = 3.0 V, CL = 5 pF - supports >200 MHz data rates in short trace applications |
| VOL (IO = 4.0 mA) | 0.50 V at VCC = 3.0 V - guarantees TTL-compatible low-level margin when driving 74LVC inputs |
| VIH / VIL | 2.0 V / 0.9 V at VCC = 3.3 V - provides 0.4 V noise margin against 3.3 V CMOS thresholds |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents bus contention during hot-swap or sleep-mode isolation |
| ESD Rating | HBM >5000 V, CDM >1000 V - meets industrial IEC 61000-4-2 system-level immunity requirements |
Pinout & Package
74AUP1G240GF,132 is supplied in SOT891 - a 5-terminal leadless plastic package measuring 1.0 × 1.0 × 0.35 mm (body), optimized for space-constrained wearables and medical patches.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable input | Active-HIGH control: drives Y to high-Z when asserted; supports shared-bus arbitration |
| 2 (A) | Inverting data input | Schmitt-triggered - rejects <100 mV noise spikes and accepts slow edges down to 200 ns/V slew rate |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output drivers; must be low-inductance for EMI control |
| 4 (Y) | Inverting 3-state output | Drives inverted A when OE = LOW; enters high-Z when OE = HIGH - eliminates bus contention |
| 5 (VCC) | Power supply | Accepts 0.8–3.6 V; includes internal regulation for stable switching across voltage scaling |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (0.8–3.6 V) | Eliminates level shifters in multi-rail systems - e.g., connects 1.1 V FPGA I/O directly to 3.3 V ADC |
| IOFF partial power-down | Blocks backflow current during VCC ramp-down or off-state, protecting upstream drivers in hot-plug modules |
| Schmitt-trigger inputs | Enables reliable detection of mechanical switch bounce or thermistor-based threshold crossings without external hysteresis |
| Overvoltage-tolerant inputs | Accepts 3.6 V signals even at VCC = 0.8 V - simplifies bidirectional level translation in USB-C CC line monitoring |
| Low dynamic power (CPD = 4.2 pF) | Reduces switching loss to <10 μW at 1 MHz/3.3 V - extends battery life in BLE beacon transceivers |
Applications
| Industrial Sensor Interface | Wearable Health Monitor |
|---|---|
Use Scenario: Isolating and inverting analog sensor output before ADC sampling in a factory vibration monitor. IC Role / Device Role / Timing Role: Signal conditioner and bus isolator - buffers noisy piezoelectric sensor output while enabling/disabling ADC clock domain via OE. Use Value: Schmitt-trigger input rejects EMI-induced glitches; IOFF prevents sensor bias leakage during MCU sleep, extending node lifetime by >30%. | Use Scenario: Driving LED indicators and enabling/disabling SPI flash memory in a compact ECG patch. IC Role / Device Role / Timing Role: Level-shifting buffer and power-gating controller - translates 1.2 V SoC GPIO to 3.0 V LED anode drive and gates flash VCC enable line. Use Value: 0.8 V minimum VCC allows direct connection to buck-boost regulator output; 0.50 V VOL ensures full brightness at 3.0 V/5 mA LED current. |
| Automotive Body Control Module | Smart Home Hub |
Use Scenario: Interfacing door-lock actuator feedback signals to a 1.8 V microcontroller in a LIN subsystem. IC Role / Device Role / Timing Role: Inverting line driver with fail-safe disable - converts open-collector lock-status signal to active-HIGH logic while disabling during ignition-off. Use Value: Overvoltage-tolerant inputs withstand 12 V transients on LIN lines; –40 °C to +125 °C rating ensures reliability under hood conditions. | Use Scenario: Managing shared I²C bus between Zigbee SoC and environmental sensors in a battery-powered smart thermostat. IC Role / Device Role / Timing Role: Bus isolator and signal inverter - separates sensor I²C lines from main SoC during firmware updates using OE-controlled high-Z state. Use Value: 2.3 ns tpd preserves I²C timing budgets at 400 kHz; 1.4 μA max ICC minimizes quiescent drain during 99% sleep duty cycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverting buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G04DBVR | No IOFF; max VCC = 5.5 V; 3.5 ns tpd at 3.3 V; no Schmitt input | Lacks partial power-down and noise immunity - unsuitable for mixed-voltage hot-swap systems | Select only if 5 V tolerance and higher drive strength (24 mA) outweigh need for ultra-low leakage and Schmitt noise rejection |
| 74LVC1G14GW,125 | Non-inverting Schmitt trigger; no 3-state; same VCC range and IOFF | Cannot replace inverting function or bus-isolation role - requires redesign of OE control logic | Choose only when signal inversion is unnecessary and continuous drive (not tri-state) is acceptable |
Compared with SN74LVC1G04DBVR and 74LVC1G14GW,125, the 74AUP1G240GF,132 uniquely combines inversion, 3-state, Schmitt input, and IOFF in one die - making it irreplaceable for low-power, noise-prone, multi-supply bus gating where functional integrity and leakage control are non-negotiable.
Availability
74AUP1G240GF,132 is available at Aetrix Electronics and suitable for industrial sensor nodes, wearable health monitors, automotive body controllers, and smart home hubs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G240GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.
The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital interfacing in battery-operated and energy-harvesting systems, emphasizing sub-1 μA static current, wide-VCC operation, and robust IO architecture.
FAQ
What is the maximum allowable input voltage when VCC = 0 V?
The 74AUP1G240GF,132 supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC state. When VCC = 0 V, VI may reach 3.6 V without damage or excessive leakage - enabling safe hot-plug insertion into live buses or level translation from higher-voltage domains without external clamping diodes.
Does this device support true bidirectional level shifting?
No - the 74AUP1G240GF,132 is unidirectional (A → Y only) and inverting. It cannot pass signals from Y to A. For bidirectional level shifting, a dedicated bus transceiver like the TXB0104 is required; this part serves only as a controlled-output buffer with direction fixed by pinout and logic function.
How does the Schmitt-trigger input improve noise immunity in sensor applications?
Schmitt-trigger inputs provide hysteresis (typically 0.3–0.5 V at 3.3 V), meaning VIH and VIL differ significantly - e.g., VIH = 2.0 V and VIL = 0.9 V at VCC = 3.3 V. This prevents multiple toggles on slowly rising/falling signals (e.g., thermistor voltage ramps), eliminating false triggers in proximity or ambient light sensing without software debouncing.
Can OE be left floating in PCB layout?
No - OE must be actively driven HIGH or LOW. The datasheet specifies an "input-disable feature" but does not guarantee defined behavior with OE floating. Uncontrolled OE states risk intermittent high-Z output, causing bus contention or undefined logic levels. Always tie OE to VCC or GND via pull-up/down resistor (e.g., 10 kΩ) unless dynamically controlled by a host processor.
74AUP1G240GF,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT891 (1x1)
74AUP1G240GF,132 FAQ
1.How can I place an order for 74AUP1G240GF,132 through Aetrix?
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6.How does Aetrix verify that 74AUP1G240GF,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G240GF,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G240GF,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G240GF,132?
All 74AUP1G240GF,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G240GF,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G240GF,132 part is unused and in its original packaging.
Return procedure for 74AUP1G240GF,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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