Nexperia USA Inc. 74AUP1G240GM,132
- Part No.:
- 74AUP1G240GM,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G240GM,132.pdf
- Description:
- IC BUF INVERT 3.6V 6XSON/SOT886
- Quantity:
- Payment:

- Shipping:

Inventory:4,853
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Product details
Overview
74AUP1G240GM,132 from Nexperia is a single-channel low-power inverting buffer/line driver with 3-state output and Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply range, delivering ICC ≤ 1.4 μA at −40 °C to +125 °C, tpd ≤ 4.6 ns at VCC = 3.3 V/CL = 5 pF, and IOFF-enabled partial power-down protection. It serves as a level-shifting signal conditioner in battery-powered sensor interfaces.
For engineers reviewing the 74AUP1G240GM,132 datasheet, 74AUP1G240GM,132 pinout, 74AUP1G240GM,132 application, or 74AUP1G240GM,132 equivalent, key selection criteria include ultra-low static current, guaranteed 3-state behavior under power-down, Schmitt-trigger noise immunity, and XSON6 (SOT886) package compatibility with high-density PCB layouts.
Technical Context
This device implements a single inverting logic gate with active-low enable control (OE), where HIGH on OE forces Y into high-impedance state. Its Schmitt-trigger inputs tolerate slow-rising signals and reject noise up to ±100 mV hysteresis margin.
The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA, and input-disable functionality permits floating input conditions without leakage escalation. All I/O pins tolerate overvoltage up to 3.6 V independent of VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - enables multi-year operation in coin-cell–powered IoT endpoints |
| tpd (VCC = 3.3 V, CL = 5 pF) | 4.6 ns - sufficient for 100 MHz data strobing in serial control buses |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents cross-conduction in hot-swap or rail-cycling systems |
| VIL / VIH Thresholds | VIL ≤ 0.3×VCC, VIH ≥ 0.7×VCC - ensures robust noise margins across full voltage range |
| ESD Rating (HBM) | 5000 V - exceeds IEC 61000-4-2 Level 4 for industrial board-level handling |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive and industrial motor-control environments |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); 6-terminal, no-lead surface-mount; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flank terminals for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data input | Inverting logic input with Schmitt-trigger hysteresis; accepts 0–3.6 V regardless of VCC |
| OE | Output enable | Active-HIGH control: OE = HIGH → Y = high-Z; OE = LOW → Y = NOT(A) |
| GND | Ground reference | 0 V return path for all internal circuitry and I/O clamp diodes |
| n.c. | No-connect terminal | Internally unconnected; must remain floating or grounded per layout best practice |
| VCC | Power supply | Primary bias rail; powers internal logic and output drivers; supports dynamic voltage scaling |
| Y | Inverting buffered output | 3-state CMOS output capable of sinking 4 mA or sourcing 4 mA at VCC = 3.0 V |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA over full temperature range enables always-on monitoring nodes |
| IOFF partial power-down | Prevents damaging back-current flow when VCC is off while I/O lines remain live |
| Schmitt-trigger inputs | Guarantees clean switching on noisy or slow-rising signals (e.g., mechanical switch debouncing) |
| Overvoltage-tolerant I/O | All pins withstand 3.6 V regardless of VCC value - simplifies mixed-voltage board design |
| JEDEC-compliant voltage ranges | Validated across JESD8-12 through JESD8-B standards - ensures interoperability with legacy and next-gen logic families |
Applications
| Industrial Sensor Interface | Low-Power Wearable Controller |
|---|---|
Use Scenario: Isolating analog sensor outputs before ADC sampling in a 1.8 V microcontroller system powered by a 3.0 V LDO. IC Role / Device Role / Timing Role: Inverting buffer with level translation and noise filtering between 3.0 V sensor domain and 1.8 V MCU GPIO. Use Value: Schmitt-trigger input rejects EMI from nearby motor drives; 3-state allows shared bus arbitration during sleep mode. | Use Scenario: Enabling/disabling LED driver enable lines in a Bluetooth LE fitness tracker with intermittent display activation. IC Role / Device Role / Timing Role: 3-state line driver controlling multiple LED anode paths via common cathode configuration. Use Value: IOFF blocks reverse current when main rail drops during deep-sleep, preserving battery charge for >3 years. |
| Automotive Body Control Module | Medical Diagnostic Handheld |
Use Scenario: Driving CAN transceiver standby control signals in a junction box module exposed to −40 °C to +125 °C ambient. IC Role / Device Role / Timing Role: Inverting buffer with OE-controlled shutdown for fail-safe isolation of transceiver during reset sequences. Use Value: Guaranteed operation at 125 °C and 3.3 V ensures reliability in engine-bay proximity; HBM 5 kV rating withstands assembly ESD events. | Use Scenario: Conditioning pushbutton inputs in a portable ECG monitor where tactile switches feed directly into a 1.2 V SoC. IC Role / Device Role / Timing Role: Input debouncer and voltage translator from 3.3 V switch pull-up to 1.2 V logic threshold. Use Value: Input-disable feature eliminates need for external pull-down resistors; <1.4 μA ICC extends battery life beyond FDA-required 12-month shelf life. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverting buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G240DBVR | Higher ICC (max 10 μA), wider VCC range (1.65–5.5 V), no IOFF, no Schmitt input | Lacks power-down safety and noise immunity; requires external hysteresis for noisy inputs | Select only if 5 V tolerance or higher drive strength (>32 mA) is required and IOFF is unnecessary |
| 74LVC1G14GW,125 | Non-inverting Schmitt trigger, no 3-state, no OE pin, same XSON6 package | Cannot perform bus isolation or tri-state control; limited to signal conditioning only | Choose when inversion is not needed and output must remain always active |
Compared with SN74LVC1G240DBVR and 74LVC1G14GW,125, the 74AUP1G240GM,132 uniquely combines ultra-low ICC, IOFF, Schmitt inputs, and 3-state control in one XSON6 footprint-making it optimal for energy-constrained, mixed-voltage, and fail-safe interface designs.
Availability
74AUP1G240GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable controller subsystems, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G240GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.
The 74AUP1G240 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-operated and thermally constrained applications demanding sub-microamp quiescent current and robust mixed-voltage interoperability.
FAQ
What is the maximum capacitive load the 74AUP1G240GM,132 can drive while maintaining specified tpd?
The device is characterized up to CL = 30 pF across all VCC and temperature ranges. At VCC = 3.3 V and Tamb = 25 °C, tpd remains ≤ 8.5 ns with 30 pF load. For reliable timing closure in high-speed routing, keep trace + load capacitance below 25 pF to maintain margin against process/voltage/temperature variation.
Can the 74AUP1G240GM,132 be used with VCC = 0 V while signals are present on A or Y pins?
Yes - the IOFF circuit actively isolates outputs when VCC = 0 V, limiting OFF-state leakage to ±0.75 μA. Inputs tolerate 0–3.6 V regardless of VCC, enabling safe "live insertion" and hot-swap operation without latch-up risk or damage.
Does the Schmitt-trigger input eliminate the need for external RC debounce circuits?
Yes - the built-in hysteresis (typically 100–200 mV) reliably rejects contact bounce and EMI on mechanical switch inputs. For switches with >10 ms bounce duration, no external RC network is required; simply connect switch between A and GND with pull-up to VCC.
Is the n.c. pin on the SOT886 package required to be left floating or may it be grounded?
The n.c. pin is internally unconnected and must be left floating per Nexperia's layout guidelines. Grounding it may induce parasitic coupling or violate package stress specifications; solder mask-defined keep-out around this terminal is recommended for reflow reliability.
74AUP1G240GM,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1G240GM,132 FAQ
1.How can I place an order for 74AUP1G240GM,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G240GM,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G240GM,132 reliable?
The price and inventory of 74AUP1G240GM,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G240GM,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1G240GM,132?
For technical support, including 74AUP1G240GM,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G240GM,132 requirements.
6.How does Aetrix verify that 74AUP1G240GM,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G240GM,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G240GM,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G240GM,132?
All 74AUP1G240GM,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G240GM,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G240GM,132 part is unused and in its original packaging.
Return procedure for 74AUP1G240GM,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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