Nexperia USA Inc. 74AUP1G240GW,125
- Part No.:
- 74AUP1G240GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G240GW,125.pdf
- Description:
- IC BUFFER INVERT 3.6V 5TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AUP1G240GW,125 from Nexperia is a single-channel low-power inverting buffer/line driver with 3-state output and Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering ICC ≤ 1.4 μA at −40 °C to +125 °C, tpd ≤ 4.6 ns at VCC = 3.3 V/CL = 5 pF, and IOFF-enabled partial power-down protection. It serves as a level-shifting signal conditioner in battery-powered sensor interfaces and I²C bus extenders.
For engineers reviewing the 74AUP1G240GW,125 datasheet, 74AUP1G240GW,125 pinout, 74AUP1G240GW,125 application, or 74AUP1G240GW,125 equivalent, key selection criteria include guaranteed 3-state isolation under VCC = 0 V, input tolerance to 3.6 V independent of VCC, sub-1 μA static current at 0.8 V, Schmitt-trigger hysteresis for noisy rail-to-rail signals, and TSSOP5 package compatibility with 0.65 mm pitch PCB layouts.
Technical Context
This device implements a single inverting logic gate with active-low 3-state control (OE), where HIGH on OE forces Y into high-impedance OFF-state. Its Schmitt-trigger inputs provide ≥ 0.3 × VCC hysteresis across all supply voltages, enabling robust operation with slow-rising signals such as those from mechanical switches or RC networks.
The IOFF circuit actively disables output leakage when VCC = 0 V, limiting backflow current to ±0.75 μA, and supports JEDEC-compliant partial power-down modes per JESD78 Class II latch-up immunity (>100 mA). All inputs tolerate up to 3.6 V regardless of VCC setting, enabling mixed-voltage domain interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - Ensures <1.5 μW static power at 1.8 V, critical for always-on IoT node wake-up circuits. |
| tpd (VCC = 3.3 V, CL = 5 pF) | 4.6 ns - Supports >100 MHz data rates in short-reach digital interconnects like display timing control. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - Prevents destructive backfeed current when hot-plugging peripheral modules powered independently. |
| Input Hysteresis | ≥0.3 × VCC - Rejects noise spikes up to 500 mV on 1.8 V rails, eliminating need for external RC filtering. |
| Overvoltage Tolerance | 3.6 V on all inputs - Allows safe connection to 3.3 V buses while operating from 1.2 V core supply. |
| Operating Temperature | −40 °C to +125 °C - Qualified for under-hood automotive body control modules and industrial motor drive feedback paths. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE (Output Enable) | Active-HIGH control: drives Y to high-Z when asserted; enables bus sharing in multi-driver systems. |
| 2 | A (Data Input) | Inverting logic input with Schmitt-trigger threshold; accepts slow edges down to 200 ns/V slew rate. |
| 3 | GND | Reference ground terminal; must be low-impedance connection to minimize switching noise coupling. |
| 4 | Y (Data Output) | Inverted, 3-state output; sinks/source up to ±4 mA at VCC = 3.3 V with VOL ≤ 0.45 V / VOH ≥ 2.3 V. |
| 5 | VCC | Power supply input; decoupling capacitor (100 nF) required within 3 mm for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA over full temperature range ensures <10 μW system standby consumption in energy-harvesting nodes. |
| IOFF partial power-down | Blocks bidirectional current flow when VCC = 0 V, enabling safe insertion/removal in live-backplane systems. |
| Schmitt-trigger inputs | Hysteresis ≥0.3 × VCC eliminates contact bounce and EMI-induced glitches on pushbutton or encoder inputs. |
| Wide voltage interoperability | 3.6 V-tolerant inputs allow direct connection to higher-voltage peripherals without external clamping diodes. |
| JEDEC-compliant ESD | HBM >5000 V and CDM >1000 V protect against assembly handling damage and field electrostatic events. |
Applications
| Industrial Sensor Interface | I²C Bus Extender |
|---|---|
Use Scenario: Signal conditioning for analog sensor outputs digitized by low-voltage microcontrollers in factory automation PLCs. IC Role / Device Role / Timing Role: Inverting buffer isolates noisy analog front-end from digital domain while providing 3-state capability for shared ADC input multiplexing. Use Value: Schmitt-trigger inputs reject 500 mV EMI spikes on long sensor cables; 0.8 V operation extends battery life in wireless node transceivers. | Use Scenario: Level translation and bus capacitance buffering between 1.8 V master and 3.3 V slave devices on extended I²C traces. IC Role / Device Role / Timing Role: Bidirectional line driver with OE-controlled 3-state output enables dynamic bus arbitration without contention. Use Value: 3.6 V-tolerant inputs accept 3.3 V slave pull-ups while powered from 1.8 V rail; tpd < 5 ns preserves I²C timing margins. |
| Automotive Body Control | Portable Medical Device |
Use Scenario: Wake-up signal routing in vehicle door module ECUs requiring ASIL-B compatible low-power logic. IC Role / Device Role / Timing Role: Inverting buffer with IOFF ensures no backfeed during sleep mode when main MCU is powered down but CAN transceiver remains active. Use Value: −40 °C to +125 °C rating meets AEC-Q100 Grade 1; IOFF leakage <1 μA prevents battery drain during 10-year parking mode. | Use Scenario: Isolating tactile button inputs in handheld diagnostic tools powered by coin-cell batteries. IC Role / Device Role / Timing Role: Debounced input conditioner converting mechanical switch bounce into clean digital transitions for ultra-low-power ARM Cortex-M0+ processors. Use Value: Sub-μA ICC at 1.2 V extends 5-year shelf life; Schmitt hysteresis eliminates need for external RC filters, reducing BOM count. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverting buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G04DBVR | No IOFF; max VCC = 5.5 V; no Schmitt inputs; ICC = 10 μA at 3.3 V | Lacks partial power-down support; requires external pull-downs for floating inputs | Select only if 5 V tolerance is mandatory and VCC never drops to 0 V during system operation. |
| 74LVC1G14GW,125 | Same package; includes Schmitt inputs; no IOFF; ICC = 2 μA at 3.3 V | Provides hysteresis but cannot prevent backfeed in hot-swap scenarios | Choose when noise immunity is primary concern and power sequencing guarantees VCC monotonicity. |
Compared with SN74LVC1G04DBVR and 74LVC1G14GW,125, the 74AUP1G240GW,125 uniquely combines sub-μA static current, IOFF-enabled backfeed blocking, and Schmitt-trigger inputs in a single TSSOP5 footprint-enabling fail-safe power-gated architectures unattainable with standard LVC variants.
Availability
74AUP1G240GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, portable medical diagnostics, and battery-powered I²C extender designs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G240GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power efficiency and reliability.
The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital signal conditioning in space-constrained, battery-operated, and thermally sensitive applications-designed specifically for energy harvesting, wearables, and automotive subsystems demanding sub-microwatt quiescent operation.
FAQ
What is the minimum supply voltage at which 74AUP1G240GW,125 guarantees logic functionality?
The device is fully specified from 0.8 V to 3.6 V, with VIH and VIL thresholds defined down to 0.8 V (VIH ≥ 0.75 × VCC, VIL ≤ 0.25 × VCC). At 0.8 V, it delivers tpd ≤ 22.3 ns and ICC ≤ 1.4 μA, making it suitable for energy-harvesting systems powered by single-cell NiMH or thin-film batteries.
Does 74AUP1G240GW,125 require external pull-up or pull-down resistors on unused inputs?
No. The input-disable feature allows floating input conditions without risk of increased ICC or undefined logic states. Internal circuitry holds unconnected inputs at valid logic levels, eliminating need for external biasing components and reducing PCB area and BOM cost in space-constrained designs.
How does the IOFF function behave when VCC is ramping during power-up or power-down sequences?
IOFF activates automatically when VCC falls below ~0.2 V, limiting VI/O leakage to ±0.75 μA even if inputs/outputs remain biased at 3.6 V. During power-up, IOFF deactivates only after VCC exceeds the functional threshold (~0.6 V), ensuring no transient backfeed occurs across the full 0 V → 0.6 V transition band.
Can 74AUP1G240GW,125 drive a 50 pF load while maintaining timing specifications?
No. The datasheet specifies dynamic performance only up to CL = 30 pF. At CL = 50 pF, propagation delay increases beyond guaranteed limits (e.g., tpd > 10 ns at VCC = 3.3 V), potentially violating setup/hold timing in high-speed interfaces. For >30 pF loads, use a higher-drive buffer or add series termination to manage edge rates.
74AUP1G240GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G240GW,125 FAQ
1.How can I place an order for 74AUP1G240GW,125 through Aetrix?
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6.How does Aetrix verify that 74AUP1G240GW,125 is sourced from the original manufacturer or authorized distributors?
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7.What is the process for return or replacement of 74AUP1G240GW,125?
All 74AUP1G240GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G240GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G240GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G240GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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