Nexperia USA Inc. 74AUP1G240GX,125
- Part No.:
- 74AUP1G240GX,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 4-XFDFN Exposed Pad
- Datasheet:
-
74AUP1G240GX,125.pdf
- Description:
- IC BUFFER INVERT 3.6V 5X2SON
- Quantity:
- Payment:

- Shipping:

Inventory:4,940
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Product details
Overview
74AUP1G240GX,125 from Nexperia is a single-channel low-power inverting buffer/line driver with 3-state output and Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply. It features output enable (OE) control, IOFF partial power-down protection, and supports industrial temperature range (−40 °C to +125 °C) in X2SON5 package. Used for signal level translation and bus isolation in ultra-low-power IoT sensor interfaces.
For engineers reviewing the 74AUP1G240GX,125 datasheet, 74AUP1G240GX,125 pinout, 74AUP1G240GX,125 application, or 74AUP1G240GX,125 equivalent, key selection criteria include its 0.9 μA max ICC at 3.6 V, 5-pin X2SON5 thermal-enhanced footprint, Schmitt-trigger noise immunity, and guaranteed IOFF operation during system power sequencing.
Technical Context
This device implements a single inverting logic gate with tristate output controlled by an active-low OE input. Its Schmitt-trigger inputs tolerate slow-rising signals and reject noise up to ±30 % of VCC, enabling robust interfacing with mechanical switches or RC-debounced sources.
The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA and preventing damage during hot-insertion or partial power-down sequences-critical for battery-backed subsystems and modular embedded designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (VCC = 3.6 V) | 0.9 μA - Ensures sub-1 μA static power draw in always-on sensor nodes or real-time clock backup paths. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - Prevents >100 μA destructive back-current during board-level power sequencing or module hot-swap. |
| tpd (VCC = 3.3 V, CL = 5 pF) | 3.6 ns - Supports clean signal buffering at >100 MHz data rates in low-voltage serial control lines. |
| Input Hysteresis | Typ. 0.1 × VCC - Rejects noise spikes up to 330 mV on 3.3 V inputs, eliminating external RC filtering in noisy industrial environments. |
| Operating Temperature | −40 °C to +125 °C - Qualified for under-hood automotive ECUs, industrial motor drives, and outdoor edge computing hardware. |
Pinout & Package
X2SON5 package (SOT1226-3): 0.8 mm × 0.8 mm × 0.32 mm body, 5-terminal no-lead thermal-enhanced outline with exposed die pad for improved heat dissipation in space-constrained PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable Input | Active-HIGH control: drives Y to high-impedance when HIGH; enables inversion when LOW. |
| 2 (A) | Data Input | Inverting logic input with Schmitt-trigger threshold; tolerant of slow edges and EMI-induced glitches. |
| 3 (GND) | Ground Reference | 0 V return path for all internal circuitry and output current; must be low-inductance connection. |
| 4 (Y) | Inverted Output | 3-state buffered output; sinks or sources up to ±4 mA at 3.3 V while maintaining VOL ≤ 0.45 V / VOH ≥ 2.3 V. |
| 5 (VCC) | Power Supply | Single-supply rail supporting 0.8–3.6 V; includes internal regulation and brown-out detection for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 0.9 μA across full VCC range - extends battery life in coin-cell-powered wearables and remote sensors. |
| IOFF partial power-down | Backflow current limited to ±0.75 μA at VCC = 0 V - eliminates need for external blocking diodes in multi-rail systems. |
| Schmitt-trigger inputs | Hysteresis ≥ 0.1 × VCC - rejects noise on long PCB traces or unshielded cables without external RC networks. |
| Overvoltage-tolerant inputs | Accepts 3.6 V inputs regardless of VCC setting - simplifies mixed-voltage interconnect between legacy 3.3 V peripherals and new 1.2 V SoCs. |
| JEDEC-compliant ESD | HBM > 5000 V, CDM > 1000 V - survives handling and assembly without special ESD controls in standard production lines. |
Applications
| Industrial Sensor Interface | Low-Power MCU GPIO Expansion |
|---|---|
Use Scenario: Connecting analog sensor output (e.g., thermistor divider) to a 1.8 V ADC input in a battery-powered environmental monitor. IC Role / Device Role / Timing Role: Inverting buffer with Schmitt-trigger input cleans noisy RC-filtered voltage and translates 3.3 V sensor swing down to 1.8 V logic levels. Use Value: Eliminates external hysteresis comparator and level shifter, reducing BOM count by two components and saving 1.2 mm² PCB area. | Use Scenario: Expanding GPIO count on a Cortex-M0+ microcontroller with limited 3.3 V I/O pins driving multiple SPI slave select lines. IC Role / Device Role / Timing Role: 3-state inverting buffer isolates unused SPI peripherals during bus arbitration, preventing contention on shared MISO/MOSI lines. Use Value: Enables dynamic peripheral enable/disable with <3.6 ns propagation delay, preserving timing margins in 20 MHz SPI systems. |
| Automotive Body Control Module | IoT Edge Node Power Sequencing |
Use Scenario: Driving LED indicators from a 5 V CAN transceiver's status outputs in a 12 V vehicle chassis environment. IC Role / Device Role / Timing Role: Level-shifting buffer with overvoltage-tolerant inputs accepts 5 V logic while powered from 3.3 V MCU rail, with IOFF protection during ignition-off state. Use Value: Avoids risk of backfeed into 3.3 V domain when 5 V transceiver remains powered, meeting ISO 16750-2 load-dump immunity requirements. | Use Scenario: Managing power-up sequence of RF SoC and sensor array in a LoRaWAN end-node where subsystems power on at different times. IC Role / Device Role / Timing Role: Tristate buffer gates communication lines between modules until both are fully powered and initialized. Use Value: Prevents undefined states and latch-up during staggered power application, verified to operate reliably at −40 °C to +125 °C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverting buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G04DBVR | No IOFF; max VCC = 5.5 V; higher ICC (10 μA typical); no Schmitt input | Requires external power sequencing control; unsuitable for partial power-down systems | Select only if 5 V tolerance and higher drive strength (>32 mA) are required and IOFF is not needed. |
| 74LVC1G14GW,125 | Non-inverting Schmitt trigger; no 3-state; same XSON6 package but 6-pin | Lacks output disable function; cannot isolate buses or share signal lines | Choose when noise immunity is critical but tristate control is unnecessary, e.g., clock conditioning or reset debouncing. |
Compared with SN74LVC1G04DBVR and 74LVC1G14GW,125, the 74AUP1G240GX,125 uniquely combines ultra-low ICC, guaranteed IOFF, Schmitt input, and 3-state output in a 5-pin X2SON5 package-making it optimal for space- and power-constrained hot-pluggable subsystems.
Availability
74AUP1G240GX,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, IoT edge node power sequencing, and low-power MCU GPIO expansion requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1G240GX,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained systems, emphasizing sub-μA static current, wide VCC range, and robust IOFF behavior for modern embedded architectures.
FAQ
What is the maximum capacitive load the 74AUP1G240GX,125 can drive while maintaining specified tpd?
The device is characterized up to 30 pF load capacitance. At VCC = 3.3 V and CL = 30 pF, tpd is 6.4 ns (max), confirming reliable operation with typical PCB trace + IC input capacitance. Exceeding 30 pF may increase propagation delay nonlinearly and degrade edge rate due to increased slew limitation.
Does the 74AUP1G240GX,125 support true bidirectional data flow?
No. It is a unidirectional inverting buffer with fixed input (A) and output (Y) terminals. The 3-state output enables bus sharing but does not allow reverse signal transmission. For bidirectional applications, a dedicated bus transceiver such as 74AUP2G241 must be used.
How does the IOFF feature behave when VCC is ramping from 0 V to nominal voltage?
IOFF activates automatically when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.5 V. During this transition, output leakage stays ≤ ±0.75 μA regardless of OE or input voltage, ensuring safe hot-plug operation without external supervision circuitry.
Can the Schmitt-trigger input be disabled to use standard CMOS thresholds?
No. The Schmitt-trigger action is inherent to the input structure and cannot be bypassed or configured. It provides fixed hysteresis (~0.1 × VCC) across the entire operating range, which is essential for noise rejection but precludes precise threshold tuning for analog comparator use cases.
74AUP1G240GX,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 4-XFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-X2SON (0.80x0.80)
74AUP1G240GX,125 FAQ
1.How can I place an order for 74AUP1G240GX,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G240GX,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G240GX,125 reliable?
The price and inventory of 74AUP1G240GX,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G240GX,125 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1G240GX,125?
For technical support, including 74AUP1G240GX,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G240GX,125 requirements.
6.How does Aetrix verify that 74AUP1G240GX,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G240GX,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G240GX,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G240GX,125?
All 74AUP1G240GX,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G240GX,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G240GX,125 part is unused and in its original packaging.
Return procedure for 74AUP1G240GX,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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