Diodes Incorporated 74AUP1G32FS3-7

Overview

74AUP1G32FS3-7 from Diodes Incorporated is a single 2-input positive OR gate in an ultra-low-power AUP CMOS logic family, operating from 0.8V to 3.6V supply, delivering ±4mA output drive at 3.0V, with IOFF partial power-down protection and Schmitt-trigger inputs (250mV hysteresis at 3.0V), deployed in battery-powered portable electronics such as e-readers and GPS navigation devices.

For engineers reviewing the 74AUP1G32FS3-7 datasheet, 74AUP1G32FS3-7 pinout, 74AUP1G32FS3-7 application, or 74AUP1G32FS3-7 equivalent, key selection criteria include its 0.8–3.6V VCC range, sub-1µA ICC static current, 2.1ns typical propagation delay at 3.3V/CL=5pF, IOFF-enabled system-level power sequencing, and X2-DFN0808-4 footprint compatibility with space-constrained PCB layouts.

Technical Context

This device implements the Boolean function Y = A + B using advanced ultra-low-power CMOS process technology, supporting full rail-to-rail input/output swing across its 0.8V–3.6V operating range. Its Schmitt-trigger inputs provide 250mV hysteresis at VCC = 3.0V, enabling robust noise immunity for slow-rising or noisy control signals in portable systems.

The IOFF circuit actively disables output leakage during partial power-down states, limiting VI/O backflow to ≤0.6µA over –40°C to +125°C, while maintaining latch-up immunity >100mA per JESD78 Class I. It is fully specified for mixed-voltage interfacing with TTL- and CMOS-compatible logic families.

Key Specifications

Pinout & Package

X2-DFN0808-4 package: 0.8mm × 0.8mm × 0.35mm body, 0.5mm diamond pad pitch, bottom-side thermal pad, no leads - optimized for minimal PCB area and high-density routing in wearables and IoT edge nodes.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with SN74LVC1G32DBVR and 74AHC1G32SE-7, the 74AUP1G32FS3-7 uniquely balances ultra-low ICC, wide VCC scalability, and IOFF protection - making it the only option qualified for long-life, multi-rail, and partial-power-down embedded systems.

Availability

74AUP1G32FS3-7 is available at Aetrix Electronics and suitable for battery-powered portable electronics, low-voltage sensor interfaces, and space-constrained IoT edge nodes requiring stable component supply and long-term lifecycle support.

Supply support for 74AUP1G32FS3-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability, energy-efficient components for consumer, industrial, and automotive markets.

The 74AUP logic family targets ultra-low-power portable applications, with design emphasis on extended battery life, mixed-voltage interoperability, and robustness in thermally constrained environments.

FAQ

What is the maximum recommended operating temperature for 74AUP1G32FS3-7?

The device is rated for continuous operation from –40°C to +125°C ambient temperature, with junction temperature up to +150°C. Thermal resistance θJA is 430°C/W for the X2-DFN0808-4 package, so derating is required above 85°C ambient if power dissipation exceeds ~10mW - verified via thermal simulation or IR imaging under actual load conditions.

Can Pin 5 (NC) be used as a thermal pad or grounded for improved heat dissipation?

No - Pin 5 is internally unconnected and must remain floating or be left un-soldered per Diodes' AP02001 layout guidelines. The X2-DFN0808-4 package has no exposed thermal pad; heat dissipation relies solely on copper traces connected to Pins 3 (GND) and 6 (VCC). Adding solder to Pin 5 risks shorting adjacent pads or compromising reliability.

Does the 74AUP1G32FS3-7 support mixed-voltage operation where A and B inputs are driven from different supply domains?

Yes - inputs tolerate VI from 0V to VCC + 0.5V, allowing A and B to originate from different voltage rails (e.g., 1.8V and 3.3V) as long as both remain within the absolute maximum rating (–0.5V to VCC + 0.5V) and do not exceed VCC + 0.5V. Output swing remains rail-to-rail relative to its own VCC.

How does the Schmitt-trigger input affect timing behavior compared to a standard CMOS input?

The 250mV hysteresis at VCC = 3.0V increases effective input noise margin but adds negligible delay - propagation delay (tpd) values in the datasheet already include Schmitt-trigger latency. Input transition rate ∆t/∆V is specified up to 200 ns/V, meaning rise/fall times slower than 600ns (for 3V swing) still guarantee clean switching without oscillation or metastability.