Diodes Incorporated 74AUP1G32FW4-7

Overview

74AUP1G32FW4-7 from Diodes Incorporated is a single 2-input positive OR gate in an X2-DFN1010-6 package, designed for ultra-low-power logic in battery-operated systems. It operates across 0.8V–3.6V supply, delivers ±4mA output drive at 3.0V, features IOFF partial power-down protection, and includes Schmitt-trigger inputs with ~250mV hysteresis at VCC = 3.0V - enabling robust signal conditioning in noisy portable electronics.

For engineers reviewing the 74AUP1G32FW4-7 datasheet, 74AUP1G32FW4-7 pinout, 74AUP1G32FW4-7 application, or 74AUP1G32FW4-7 equivalent, this device is selected for low-voltage logic interfacing, level translation between mixed-supply domains, and input debouncing in space-constrained IoT sensors and wearables where static current <0.9µA and dynamic CPD = 6.3pF are critical.

Technical Context

The 74AUP1G32FW4-7 implements standard Boolean OR logic (Y = A + B) using Advanced Ultra Low Power CMOS technology. Its IOFF circuit actively disables outputs during power-down to prevent backflow current, supporting hot-swap and partial-power-down system architectures.

Schmitt-trigger inputs provide noise immunity with defined hysteresis (~250mV at 3.0V), allowing reliable operation with slow-rising signals. Propagation delay ranges from 1.0ns (typ, 3.3V, CL=5pF) to 8.5ns (max, 3.3V, CL=30pF), scaling predictably with load capacitance and supply voltage.

Key Specifications

Pinout & Package

X2-DFN1010-6 package: 1.0mm × 1.0mm × 0.4mm body, 0.35mm pad pitch, no leads, bottom thermal pad, moisture sensitivity level 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with SN74LVC1G32DBVR and 74AHC1G32SE-7, the 74AUP1G32FW4-7 uniquely delivers sub-1µA static current, 0.8V compatibility, IOFF protection, and Schmitt inputs in a 1.0mm² DFN - making it the sole option for ultra-low-power, mixed-voltage, and partial-power-down designs.

Availability

74AUP1G32FW4-7 is available at Aetrix Electronics and suitable for battery-powered wearables, IoT edge sensors, and portable medical devices requiring stable component supply with long-term lifecycle assurance.

Supply support for 74AUP1G32FW4-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability, low-power, and small-footprint solutions for consumer, industrial, and automotive markets.

The 74AUP logic family targets ultra-low-power portable electronics, delivering sub-1µA static current and extended battery life through optimized CMOS process and circuit architecture.

FAQ

What is the maximum recommended load capacitance for stable 74AUP1G32FW4-7 operation?

The device is characterized up to 30pF load capacitance, with propagation delay increasing predictably (e.g., 1.0ns typ at 5pF → 8.5ns max at 30pF, 3.3V). For reliable timing closure beyond 30pF, add series resistance or use a buffer stage - the gate itself does not specify absolute maximum CL, but performance degrades linearly beyond tested conditions.

Can 74AUP1G32FW4-7 inputs be left floating in a powered system?

No. Per datasheet Note 8, unused inputs must be tied to VCC or GND. Floating inputs cause increased ICC, potential oscillation due to intermediate voltage biasing, and elevated dynamic power consumption - all violating the ultra-low-power design intent and risking functional instability.

Does the NC pin (Pin 5) require any PCB layout treatment?

Pin 5 is unconnected internally and must remain unbonded. Diodes Incorporated recommends leaving it floating - neither grounding nor connecting it to VCC. PCB layout should avoid solder mask openings or copper traces under this pad to prevent unintended coupling or shorting during reflow.

How does IOFF behavior affect system-level power sequencing?

When VCC = 0V, IOFF disables the output stage, limiting leakage to ≤0.6µA even if A, B, or Y pins are held at valid logic levels by other powered circuits. This enables safe "asynchronous power-down" - e.g., turning off a microcontroller's VCC while keeping sensor interfaces active - without risk of damaging back-current or bus contention.