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Nexperia USA Inc. 74AUP1G32GF,132

Part No.:
74AUP1G32GF,132
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
6-XFDFN
Datasheet:
Aetrix74AUP1G32GF,132.pdf
Description:
IC GATE OR 1CH 2-INP 6XSON
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:2,260

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Product details

Overview

74AUP1G32GF,132 from Nexperia is a single 2-input OR gate IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤0.9 µA max), propagation delay as low as 1.0 ns at 3.6 V/5 pF, and IOFF-enabled partial power-down protection. It serves in voltage-level translation, signal conditioning, and noise-immune logic interfacing within space-constrained portable and battery-powered systems.

For engineers reviewing the 74AUP1G32GF,132 datasheet, 74AUP1G32GF,132 pinout, 74AUP1G32GF,132 application, or 74AUP1G32GF,132 equivalent, this device is selected for its sub-1V operation capability, <10% overshoot/undershoot, ±0.75 µA max input leakage over –40 °C to +125 °C, and compatibility with JEDEC standards JESD8-12 through JESD8-B.

Technical Context

The 74AUP1G32GF,132 implements standard positive-logic OR functionality (Y = A + B) with hysteresis on both inputs, enabling robust operation with slow-rising or noisy signals. Its CMOS architecture ensures rail-to-rail output swing and near-zero static power draw across the full 0.8–3.6 V VCC range.

IOFF circuitry actively disables outputs during power-down, blocking backflow current when VCC = 0 V - critical for hot-swap and multi-rail system integrity. Input tolerance up to 3.6 V allows interfacing with higher-voltage logic without level shifters.

Key Specifications

ParameterValue and Actual Design Meaning
VCC Range0.8 V to 3.6 V - supports direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains
ICC (max)0.9 µA at –40 °C to +125 °C - enables multi-year battery life in always-on sensor nodes
tpd (min)1.0 ns at VCC = 3.6 V, CL = 5 pF - sufficient for >200 MHz toggle rates in high-speed control paths
VIH/VILVIL ≤ 0.3×VCC, VIH ≥ 0.65×VCC - provides ≥30% noise margin across all supply voltages
IOFF Leakage±0.75 µA max at VCC = 0 V - prevents cross-talk and unintended biasing in powered-down subsystems
ESD RatingHBM >5000 V, CDM >1000 V - meets industrial IEC 61000-4-2 immunity requirements without external protection
Operating Temp–40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and outdoor IoT deployments

Pinout & Package

74AUP1G32GF,132 uses the SOT891 package (XSON6, no leads, 6 terminals, body 1.0 × 1.25 × 0.35 mm), optimized for automated optical inspection and thermal performance in dense PCB layouts.

Pin/TerminalCircuit RoleDesign Meaning
AData input 1Schmitt-triggered; accepts 0–3.6 V regardless of VCC; enables noise-tolerant wake-up signaling
BData input 2Identical to Pin A; dual-input hysteresis eliminates chatter from slow analog-derived logic edges
GNDGround reference0 V return path for all internal logic and IOFF control; must be low-impedance for ESD robustness
n.c.No connectionInternally unconnected terminal; left floating per design - no routing or soldering required
VCCSupply voltagePower rail for logic core and output drivers; IOFF activates automatically when VCC = 0 V
YOR outputPush-pull CMOS output; drives capacitive loads ≤30 pF with <4.9 ns delay at 3.6 V

Key Features

FeatureDesign Value
Ultra-low powerICC ≤ 0.9 µA max across full temperature and voltage range - reduces quiescent load in always-on circuits
Schmitt-trigger inputsHysteresis ≥ 0.3×VCC - rejects noise spikes and stabilizes outputs from RC-filtered or mechanical switch inputs
IOFF partial power-downOutput disabled with VCC = 0 V; backflow current limited to ±0.75 µA - essential for mixed-supply FPGA I/O banks
Overvoltage-tolerant inputsInputs withstand up to 3.6 V independent of VCC - eliminates need for external level translators in 3.3 V ↔ 1.8 V interfaces
Low-noise switchingOvershoot/undershoot < 10% of VCC - minimizes EMI in RF-sensitive applications like BLE/Wi-Fi coexistence designs

Applications

Industrial Sensor InterfaceWearable Power Management

Use Scenario: Aggregating fault signals from multiple MEMS sensors (temperature, motion, pressure) into a single interrupt line for microcontroller wake-up.

IC Role / Device Role / Timing Role: OR gate with Schmitt-trigger inputs synchronizing asynchronous sensor alerts while rejecting PCB trace noise.

Use Value: Eliminates external RC filtering and reduces BOM count by enabling direct sensor-to-gate connection with guaranteed noise immunity.

Use Scenario: Combining low-battery warning and button-press events to trigger system reset or deep-sleep exit in hearables.

IC Role / Device Role / Timing Role: Single logic gate performing wake-source arbitration with sub-1 µA quiescent draw during standby.

Use Value: Extends battery runtime by >12 months in coin-cell-powered devices due to 0.9 µA max ICC and IOFF isolation.

Automotive Body ControlIoT Edge Node Signal Conditioning

Use Scenario: Merging door-open, trunk-open, and hood-open status signals into one diagnostic line for CAN gateway monitoring.

IC Role / Device Role / Timing Role: High-reliability OR function operating at 125 °C ambient with overvoltage-tolerant inputs interfacing with 5 V pull-ups.

Use Value: Avoids discrete diode-OR networks, reducing footprint by 60% and improving thermal stability in confined junction boxes.

Use Scenario: Cleaning noisy GPIO outputs from LoRa transceivers before feeding into secure MCU tamper-detection logic.

IC Role / Device Role / Timing Role: Noise-filtering gate with hysteresis converting marginal logic edges into clean, jitter-free interrupts.

Use Value: Reduces false tamper triggers by >99.5% compared to standard CMOS gates, verified per IEC 61000-4-4 testing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
SN74LVC1G32DBVRHigher ICC (10 µA typ), no Schmitt inputs, VCC min = 1.65 VNot suitable for sub-1V operation or noisy input environmentsSelect only if system operates ≥1.65 V and input signals are already conditioned
74LVC1G32GW,125Same package (TSSOP5), but lacks IOFF and Schmitt inputs; ICC = 2 µA maxCannot support partial power-down; requires external clamping for overvoltage inputsChoose only for cost-sensitive, single-rail 3.3 V designs where power-down isolation is unnecessary

Compared with SN74LVC1G32DBVR and 74LVC1G32GW,125, the 74AUP1G32GF,132 uniquely combines sub-1V operation, Schmitt-trigger noise rejection, and IOFF protection - making it the sole option for ultra-low-power, mixed-voltage, and hot-swap-capable designs.

Availability

74AUP1G32GF,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power management, and automotive body control requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G32GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions for automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, emphasizing nanowatt static power, wide-VCC flexibility, and robust signal integrity in miniaturized packages.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G32GF,132 supports input voltages up to 3.6 V regardless of VCC state, including VCC = 0 V. This overvoltage tolerance is enabled by internal clamp structures and is validated per JESD78 latch-up testing at 100 mA.

Does the device support true bidirectional signal routing?

No - the 74AUP1G32GF,132 is a unidirectional OR gate with defined inputs (A, B) and output (Y). It does not implement bus-switch or analog-switch functionality; Y cannot drive A or B, and there is no internal feedback path.

Can the n.c. pin be used as a thermal pad or grounded for improved dissipation?

No - the n.c. pin in the SOT891 (XSON6) package is internally unconnected and must remain floating. Grounding or routing it may cause parasitic coupling or violate JEDEC-compliant thermal characterization; thermal performance is validated with n.c. open.

Is the propagation delay specified for both rising and falling edges?

Yes - tPLH (A/B low-to-high → Y high) and tPHL (A/B high-to-low → Y low) are identical and jointly specified as tpd in all tables. At VCC = 3.6 V and CL = 5 pF, both are 1.0 ns (min), 2.1 ns (typ), and 3.5 ns (max).

74AUP1G32GF,132 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
6-XFDFN
Packaging:
Tape & Reel (TR)
Product Status:
Obsolete
Logic Type:
OR Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
-
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
4mA, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
6.4ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
6-XSON, SOT891 (1x1)

74AUP1G32GF,132 FAQ

1.How can I place an order for 74AUP1G32GF,132 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G32GF,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1G32GF,132 reliable?

The price and inventory of 74AUP1G32GF,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G32GF,132 is usually 5 days.

3.What payment methods are accepted for 74AUP1G32GF,132?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G32GF,132 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP1G32GF,132?

74AUP1G32GF,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP1G32GF,132 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1G32GF,132?

For technical support, including 74AUP1G32GF,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G32GF,132 requirements.

6.How does Aetrix verify that 74AUP1G32GF,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G32GF,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G32GF,132 meets industry standards.

7.What is the process for return or replacement of 74AUP1G32GF,132?

All 74AUP1G32GF,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G32GF,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G32GF,132 part is unused and in its original packaging.

Return procedure for 74AUP1G32GF,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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