Nexperia USA Inc. 74AUP1G32GM,115

Overview

74AUP1G32GM,115 from Nexperia is a single 2-input OR gate in XSON6 (SOT886) package, operating from 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C - used in low-voltage logic interfacing, battery-powered sensor nodes, and level-shifting I/O buffers.

For engineers reviewing the 74AUP1G32GM,115 datasheet, 74AUP1G32GM,115 pinout, 74AUP1G32GM,115 application, or 74AUP1G32GM,115 equivalent, this device serves as an ultra-low-power combinational logic element where supply voltage flexibility, sub-1 µA static current, and robust input tolerance are critical selection criteria.

Technical Context

The 74AUP1G32GM implements standard positive-logic OR functionality (Y = A + B) with Schmitt-trigger inputs that provide hysteresis (typically 0.1 × VCC), enabling reliable operation with slow-rising or noisy signals. Its CMOS design ensures rail-to-rail output swing and near-zero static current across the full 0.8–3.6 V range.

IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 µA max at 125 °C - a key requirement for hot-swap and multi-rail system partitioning. Propagation delay ranges from 0.9 ns (VCC = 3.3 V, CL = 5 pF) to 8.5 ns (VCC = 1.2 V, CL = 30 pF) over temperature.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body size 1.0 × 1.45 × 0.5 mm; wettable flanks not present; thermal pad absent; pin 1 indicator located on lower-left corner below marking code "pG".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with SN74LVC1G32DBVR and 74LVC1G32GW,125, the 74AUP1G32GM,115 uniquely delivers sub-µA static current, IOFF, and Schmitt inputs in the smallest XSON6 footprint - making it optimal for energy-critical, space-constrained, and multi-rail systems.

Availability

74AUP1G32GM,115 is available at Aetrix Electronics and suitable for industrial sensor nodes, automotive body electronics, and wearable medical devices requiring stable component supply across extended temperature and long product lifecycles.

Supply support for 74AUP1G32GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions - serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and thermally constrained applications where nanowatt static power, wide VCC range, and robust IO behavior are mandatory design requirements.

FAQ

Can 74AUP1G32GM,115 operate reliably at 0.85 V supply?

Yes. The device is fully specified down to 0.8 V, with VIH/VIL thresholds scaling proportionally (e.g., VIH ≥ 0.70 × VCC). At 0.85 V, propagation delay is ≤10.9 ns (CL = 5 pF), and ICC remains ≤1.4 µA - confirmed across –40 °C to +125 °C per datasheet Table 7 and Table 9.

Is pin 5 (n.c.) required to be grounded or left floating?

Pin 5 is internally unconnected and must remain floating - no PCB trace, solder mask opening, or thermal relief should be applied. Connecting it risks internal damage or undefined behavior, as explicitly stated in Section 6.2 of the datasheet.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes. IOFF engages whenever VCC falls to 0 V (or near 0 V), disabling the output driver and limiting leakage to ±0.75 µA max. No external control signal is needed - the circuitry is intrinsic to the silicon design and functions across the full –40 °C to +125 °C range.

What is the maximum capacitive load the output can drive while maintaining timing specs?

The device is characterized up to 30 pF (Table 8–9). At VCC = 3.3 V and Tamb = 25 °C, tpd remains ≤4.9 ns with CL = 30 pF. Driving >30 pF increases delay nonlinearly and may violate setup/hold margins - external buffering is recommended beyond this limit.