Nexperia USA Inc. 74AUP1G32GM-Q100X
- Part No.:
- 74AUP1G32GM-Q100X
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G32GM-Q100X.pdf
- Description:
- IC GATE OR 1CH 2-INP 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:14,361
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Product details
Overview
74AUP1G32GM-Q100 from Nexperia is an automotive-qualified, single 2-input OR gate in XSON6 (SOT886) package, operating across 0.8 V–3.6 V supply with Schmitt-trigger inputs for noise immunity and IOFF circuitry enabling partial power-down mode. It delivers propagation delay as low as 1.0 ns at 3.6 V/25 °C (CL = 5 pF) and static ICC ≤ 1.4 µA over –40 °C to +125 °C, used in automotive body control modules for signal-level logic combining.
For engineers reviewing the 74AUP1G32GM-Q100 datasheet, 74AUP1G32GM-Q100 pinout, 74AUP1G32GM-Q100 application, or 74AUP1G32GM-Q100 equivalent, key selection criteria include its AEC-Q100 Grade 1 qualification, ultra-low power consumption at sub-1-V operation, IOFF-enabled system-level power sequencing, and Schmitt-trigger input tolerance to slow-rising signals in noisy automotive environments.
Technical Context
This device implements a single 2-input positive-logic OR function with Schmitt-trigger inputs-ensuring hysteresis of typically 0.1 × VCC-enabling robust operation with slow or noisy input edges across its full 0.8 V–3.6 V VCC range. Input voltage tolerance extends to 3.6 V independent of VCC, supporting mixed-voltage interfacing.
The IOFF circuit actively disables outputs during power-down, limiting backflow current to ±0.75 µA (VCC = 0 V), satisfying partial power-down requirements in multi-rail automotive subsystems. Dynamic performance is characterized up to 30 pF load, with tpd ranging from 1.0 ns (3.6 V, CL = 5 pF) to 8.5 ns (3.0 V, CL = 30 pF, –40 °C to +125 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Propagation Delay (tpd) | 1.0 ns (typ, VCC = 3.6 V, CL = 5 pF, 25 °C) - Supports high-speed signal routing in timing-critical automotive control paths. |
| ICC (max) | 1.4 µA at –40 °C to +125 °C - Ensures negligible quiescent current impact on battery-powered always-on modules. |
| IOFF Leakage | ±0.75 µA at VCC = 0 V - Prevents damaging back-current during hot-swap or staggered power sequencing in domain-isolated ECUs. |
| Input Hysteresis | Typically 0.1 × VCC - Rejects noise spikes up to 360 mV (at 3.6 V), eliminating false triggering in engine bay wiring harnesses. |
| ESD Rating | HBM > 5000 V, CDM > 1000 V - Meets stringent automotive ESD immunity requirements per ISO 10605. |
| Operating Temp | –40 °C to +125 °C - Qualified for under-hood placement in powertrain and chassis control units. |
Pinout & Package
XSON6 (SOT886) package: plastic extremely thin small outline, no leads, 6 terminals, body size 1.0 mm × 1.45 mm × 0.5 mm, thermal enhanced, side-wettable flanks not present (distinct from XSON5).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | B | Second data input; accepts voltages up to 3.6 V regardless of VCC, enabling flexible inter-voltage-domain signal injection. |
| 2 | A | Primary data input; Schmitt-triggered to suppress noise-induced glitches on long PCB traces or cable-connected sensors. |
| 3 | GND | Dedicated ground reference; low-inductance connection critical for maintaining noise margin and stable IOFF behavior. |
| 4 | Y | OR output; drives capacitive loads up to 30 pF while maintaining < 4.6 ns max tpd across full temperature and voltage range. |
| 5 | n.c. | No-connect terminal; electrically isolated and must remain unconnected to avoid parasitic coupling or ESD path disruption. |
| 6 | VCC | Supply rail; supports dynamic decoupling via local 100 nF ceramic capacitor due to low internal impedance and fast transient response. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for continuous operation from –40 °C to +125 °C ambient, meeting automotive reliability and lifetime requirements. |
| Schmitt-trigger inputs | Input hysteresis ≥ 0.1 × VCC ensures clean logic transitions even with slew rates as low as 200 ns/V - critical for resistive sensor interfaces. |
| IOFF partial power-down | Output high-impedance state activated when VCC = 0 V, blocking back-current flow in multi-supply systems during sleep/wake transitions. |
| Wide VCC compatibility | Operates down to 0.8 V - supports next-generation ultra-low-power microcontrollers and always-on wake-up logic in battery management ICs. |
| Low dynamic power | CPD = 3.9 pF (VCC = 3.6 V) enables sub-µW dynamic dissipation at 1 MHz, reducing self-heating in densely packed modules. |
Applications
| Body Control Module (BCM) | Advanced Driver Assistance Systems (ADAS) Sensor Interface |
|---|---|
|
Use Scenario: Combining door-open and seat-belt-unlatched signals to trigger interior lighting and warning chime. IC Role / Device Role / Timing Role: Single OR gate performing real-time Boolean combination of two asynchronous safety-critical inputs. Use Value: Eliminates need for MCU GPIO polling; reduces latency to < 5 ns and removes software overhead in ASIL-B-relevant functions. |
Use Scenario: Merging fault flags from dual redundant radar transceivers before feeding to central ADAS controller. IC Role / Device Role / Timing Role: Hardware-level fault-or logic ensuring immediate fail-safe assertion without processor involvement. Use Value: Guarantees sub-10 ns fault propagation - faster than software-based voting - meeting ISO 26262 diagnostic response time targets. |
| Electric Power Steering (EPS) ECU | Automotive Infotainment Power Sequencing |
|
Use Scenario: OR-ing torque sensor error and motor phase current fault signals to initiate immediate torque cut-off. IC Role / Device Role / Timing Role: Safety-critical hardware interlock gate placed in the torque disable path, upstream of MCU intervention. Use Value: Provides deterministic, zero-latency fault escalation independent of firmware execution state or watchdog status. |
Use Scenario: Enabling main SoC power rail only after both PMIC OK and display panel ready signals are asserted. IC Role / Device Role / Timing Role: Power-enable combiner implementing "ready AND ready" logic using active-high OR with inverted inputs. Use Value: Reduces BOM count by replacing discrete diode-OR or dedicated power sequencer IC in cost-sensitive infotainment head units. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G32GV-Q100 | Higher ICC (max 40 µA vs. 1.4 µA), no Schmitt inputs, same XSON5 package but 5-pin vs. 6-pin pinout. | Lacks noise immunity for slow-rising sensor signals; unsuitable where input edge rate < 100 ns/V. | Select only if lowest-cost OR gate suffices and system noise environment is controlled (e.g., board-level digital interconnect). |
| SN74AUP1G32DSFR | Same core specs but non-automotive (no AEC-Q100), rated –40 °C to +85 °C only, SON6 package identical footprint. | Not qualified for under-hood or safety-critical use; requires revalidation for automotive production. | Acceptable for prototyping or non-safety automotive subsystems (e.g., HVAC control) where qualification overhead is prohibitive. |
Compared with 74LVC1G32GV-Q100 and SN74AUP1G32DSFR, the 74AUP1G32GM-Q100 uniquely combines AEC-Q100 Grade 1, Schmitt-trigger inputs, and sub-µA static current - making it the sole choice for noise-prone, always-on, safety-relevant automotive logic nodes.
Availability
74AUP1G32GM-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, ADAS sensor fusion units, and electric power steering ECUs requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for 74AUP1G32GM-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance, high-reliability logic, analog, and discrete components, with global R&D and manufacturing facilities focused on automotive and industrial markets.
The 74AUP (Advanced Ultra-low Power) product line is engineered specifically for automotive and portable applications demanding nanowatt static power, wide VCC scalability, and robust noise immunity - targeting ECU, sensor interface, and power management subsystems.
FAQ
Does 74AUP1G32GM-Q100 support 0.8 V logic levels with guaranteed timing?
Yes. The device is fully characterized down to 0.8 V VCC, with propagation delay specified at 16.8 ns (typ) for CL = 5 pF and 25 °C. Static parameters including VIH/VIL thresholds scale with VCC, ensuring functional correctness and timing predictability across the entire 0.8 V–3.6 V range.
Can Pin 5 (n.c.) be grounded or left floating in PCB layout?
Pin 5 is a no-connect terminal with no internal connection. It must remain unconnected - neither grounded nor tied to any net - to prevent unintended parasitic coupling, ESD path alteration, or mechanical stress on the die attach. Datasheet Figure 6 explicitly shows it as electrically isolated.
How does IOFF behave when VCC ramps from 0 V to nominal voltage?
IOFF remains active until VCC exceeds ~0.2 V; output stays high-impedance through the entire power-up sequence. Once VCC ≥ 0.2 V, normal logic operation begins. This ensures glitch-free enablement and eliminates backfeed risk during staggered supply ramping in multi-rail automotive ECUs.
Is the XSON6 (SOT886) package compatible with standard reflow profiles for lead-free assembly?
Yes. The SOT886 package is qualified for JEDEC J-STD-020D-compliant lead-free reflow, with peak temperature rating of 260 °C. Its 0.5 mm profile and thermal mass support uniform heating; recommended stencil aperture is 0.3 mm × 0.8 mm with 50 µm thickness for optimal solder joint formation on side-wettable-flank–free variants.
74AUP1G32GM-Q100X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.4ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1G32GM-Q100X FAQ
1.How can I place an order for 74AUP1G32GM-Q100X through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G32GM-Q100X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G32GM-Q100X reliable?
The price and inventory of 74AUP1G32GM-Q100X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G32GM-Q100X is usually 5 days.
3.What payment methods are accepted for 74AUP1G32GM-Q100X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G32GM-Q100X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G32GM-Q100X?
74AUP1G32GM-Q100X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G32GM-Q100X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G32GM-Q100X?
For technical support, including 74AUP1G32GM-Q100X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G32GM-Q100X requirements.
6.How does Aetrix verify that 74AUP1G32GM-Q100X is sourced from the original manufacturer or authorized distributors?
All 74AUP1G32GM-Q100X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G32GM-Q100X meets industry standards.
7.What is the process for return or replacement of 74AUP1G32GM-Q100X?
All 74AUP1G32GM-Q100X units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G32GM-Q100X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G32GM-Q100X part is unused and in its original packaging.
Return procedure for 74AUP1G32GM-Q100X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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