NXP Semiconductors 74AUP1G32GN,132

Overview

74AUP1G32GN,132 from Nexperia is a single 2-input OR gate in XSON6 package (SOT1115), operating from 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. It delivers ultra-low static current (≤1.4 µA max) and propagation delay as low as 0.9 ns at 3.0 V with 5 pF load, enabling use in battery-powered sensor interface logic and voltage-level agnostic control signal routing.

For engineers reviewing the 74AUP1G32GN,132 datasheet, 74AUP1G32GN,132 pinout, 74AUP1G32GN,132 application, or 74AUP1G32GN,132 equivalent, key selection criteria include its 0.9 × 1.0 × 0.35 mm XSON6 footprint, IOFF-enabled hot-swap compatibility, Schmitt-trigger input hysteresis (≥0.3×VCC), and guaranteed sub-5 ns propagation across full temperature and voltage range.

Technical Context

This device implements standard positive-logic OR functionality (Y = A + B) with Schmitt-trigger inputs that provide hysteresis of ≥0.3×VCC, enabling robust operation with slow-rising signals and high noise immunity. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.

Designed for mixed-voltage system interfacing, it supports rail-to-rail input tolerance up to 3.6 V independent of VCC, and meets JEDEC standards JESD8-12 through JESD8-B across five VCC ranges. Static power consumption remains ≤1.4 µA over –40 °C to +125 °C, while dynamic performance scales predictably with supply voltage and load capacitance.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6 terminals, body dimensions 0.9 mm × 1.0 mm × 0.35 mm, thermal pad optional, side-wettable flanks not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with 74LVC1G32GW,125 and SN74AUP1G32DBVR, the 74AUP1G32GN,132 uniquely combines ultra-miniature XSON6 packaging, guaranteed sub-1.4 µA ICC at 125 °C, and IOFF-enabled system-level power domain isolation - critical for next-generation battery-operated and automotive electronics.

Availability

74AUP1G32GN,132 is available at Aetrix Electronics and suitable for automotive body control, industrial sensor fusion, portable medical monitoring, and smart home hub designs requiring stable component supply, long-term lifecycle support, and AEC-Q200-aligned reliability.

Supply support for 74AUP1G32GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components - including logic, discrete, and MOSFET devices - with leadership in miniaturized, low-power, and high-reliability solutions.

The 74AUP (Advanced Ultra-low Power) logic family targets space- and energy-constrained applications such as wearables, automotive ECUs, and industrial IoT edge nodes where minimal footprint, wide VCC flexibility, and robust power sequencing are mandatory.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G32GN,132 allows input voltages up to 3.6 V even when VCC = 0 V, thanks to overvoltage-tolerant input structures. This enables safe connection to live buses during power-down sequences without risk of damage or leakage, as confirmed in Table 5 (VI input voltage limit: –0.5 V to +4.6 V) and Section 2 features.

Does the n.c. pin (Pin 5) require any PCB layout treatment?

No. Pin 5 is internally unconnected and must remain floating - no solder mask opening, copper pour, or trace is needed. The datasheet explicitly defines it as "not connected" in Table 3, and Nexperia's SOT1115 package drawings show no internal bond wire or die connection to this terminal.

How does IOFF behave during VCC ramp-up or ramp-down transitions?

IOFF activates automatically when VCC falls below ~0.2 V and deactivates when VCC rises above ~0.4 V, as verified by ΔIOFF test data in Table 7. During transition, output impedance exceeds 100 MΩ, preventing current flow between A/B and Y - critical for glitch-free hot-plug operation in modular systems.

Can this device drive a 10 pF load at 1.2 V while staying within propagation delay specs?

Yes. At VCC = 1.2 V and CL = 10 pF, tpd is specified as 2.3 ns (min) to 13.8 ns (max) over –40 °C to +85 °C (Table 9), and 2.3 ns to 15.2 ns over –40 °C to +125 °C. These values are fully characterized and guaranteed, enabling reliable timing closure in 1.2 V FPGA I/O banks and ultra-low-voltage microcontrollers.