Nexperia USA Inc. 74AUP1G32GS,132

Overview

74AUP1G32GS,132 from Nexperia is a single 2-input OR gate in XSON6 package (SOT1202), operating from 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. It delivers ultra-low static current (≤1.4 µA max) and propagation delay as low as 0.9 ns at 3.6 V with 5 pF load, enabling use in battery-powered sensor interfaces and low-voltage logic translation.

For engineers reviewing the 74AUP1G32GS,132 datasheet, 74AUP1G32GS,132 pinout, 74AUP1G32GS,132 application, or 74AUP1G32GS,132 equivalent, this device serves as a drop-in logic-level combiner in space-constrained, wide-VCC industrial control nodes, wearables, and IoT edge sensors where input rise/fall time tolerance and zero-power-down leakage (<±0.75 µA) are critical selection criteria.

Technical Context

This device implements a standard positive-logic OR function (Y = A + B) with Schmitt-trigger inputs that provide hysteresis (typically 0.1 × VCC), ensuring robust switching under slow or noisy signal edges. Its IOFF circuit actively disables outputs during VCC = 0 V, blocking backflow current and enabling hot-swap and partial-power-down system architectures.

All electrical characteristics-including VIH/VIL thresholds, VOH/VOL levels, propagation delay (tpd), and power dissipation capacitance (CPD = 3.9 pF typical at 3.6 V)-are fully specified across the full –40 °C to +125 °C temperature range and entire 0.8–3.6 V supply range, supporting design reuse in automotive under-hood and industrial automation environments.

Key Specifications

Pinout & Package

XSON6 package (SOT1202): 1.0 mm × 1.0 mm × 0.35 mm body, no leads, 6 terminals, thermal-enhanced plastic construction with wettable flanks optional (not on GS variant). Pin 1 indicator located on lower-left corner below marking code "pG".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with SN74LVC1G32DBVR and 74LVC1G32GW,125, the 74AUP1G32GS,132 uniquely combines sub-1 V operation, Schmitt inputs, and IOFF-making it the sole option for energy-harvesting sensors, multi-rail hot-swap controllers, and automotive body electronics requiring guaranteed noise immunity and zero-power isolation.

Availability

74AUP1G32GS,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power management, automotive body control modules, and IoT edge node wake-up logic requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G32GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in high-volume applications.

The 74AUP (Advanced Ultra-low Power) logic family targets space- and power-constrained systems such as wearables, IoT endpoints, and automotive ECUs-designed specifically to replace discrete logic while meeting stringent AEC-Q100, JEDEC, and IEC reliability standards.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G32GS,132 allows input voltages up to 3.6 V even with VCC = 0 V, thanks to overvoltage-tolerant input structures. This enables safe interfacing with powered peripherals while the gate's supply is off-critical for hot-plug and partial-power-down architectures.

Does the device require external pull-up or pull-down resistors on inputs?

No external biasing is required. The Schmitt-trigger inputs have defined thresholds (VIH ≥0.65×VCC, VIL ≤0.35×VCC) and high impedance (II ≤±0.75 µA), making them compatible with open-drain, CMOS, and TTL sources without pull resistors-reducing component count and board space.

Can Pin 5 (n.c.) be connected to GND or VCC for improved thermal performance?

No. Pin 5 is internally unconnected and must remain floating per Nexperia's design specification. Connecting it to any potential violates the SOT1202 package qualification and may cause unpredictable behavior or increased leakage due to internal coupling paths.

How does IOFF behave during VCC ramp-up or ramp-down transitions?

The IOFF circuit activates automatically when VCC drops below ~0.2 V and deactivates when VCC rises above ~0.4 V. During transition, output impedance remains high (>100 MΩ), preventing shoot-through or backfeed-verified across –40 °C to +125 °C per JEDEC JESD78 latch-up testing.