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Nexperia USA Inc. 74AUP1G32GW,125

Part No.:
74AUP1G32GW,125
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
5-TSSOP, SC-70-5, SOT-353
Datasheet:
Aetrix74AUP1G32GW,125.pdf
Description:
IC GATE OR 1CH 2-INP 5TSSOP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:12,779

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Product details

Overview

74AUP1G32GW,125 from Nexperia is a single 2-input OR gate in TSSOP5 (SOT353-1) package with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering propagation delay as low as 1.0 ns at 3.6 V/CL = 5 pF, and ICC ≤ 0.9 µA max across –40 °C to +125 °C - used in low-power logic interfacing for battery-powered sensor nodes.

For engineers reviewing the 74AUP1G32GW,125 datasheet, 74AUP1G32GW,125 pinout, 74AUP1G32GW,125 application, or 74AUP1G32GW,125 equivalent, this device is selected for ultra-low static power, partial power-down capability via IOFF, high noise immunity, and compatibility with mixed-voltage I/O systems down to 0.8 V.

Technical Context

The 74AUP1G32GW implements standard positive-logic OR functionality (Y = A + B) with Schmitt-trigger inputs enabling robust operation with slow-rising or noisy signals. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.

It supports full rail-to-rail input tolerance up to 3.6 V independent of VCC, meets JEDEC standards JESD8-12 through JESD8-B across five voltage bands, and delivers guaranteed timing performance from –40 °C to +125 °C with CL-dependent propagation delays ranging from 0.9 ns to 8.5 ns.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage Range 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters.
Max ICC (Static) 0.9 µA at –40 °C to +125 °C - ensures negligible quiescent current in always-on monitoring circuits.
tpd (A/B → Y) 1.0 ns min / 3.5 ns max at VCC = 3.0–3.6 V, CL = 5 pF - supports >200 MHz toggle rates in low-capacitance signal paths.
IOFF Leakage ±0.75 µA max at VCC = 0 V - prevents cross-conduction and bus contention in hot-swap or partial-power-down subsystems.
Input Voltage Tolerance –0.5 V to +4.6 V - allows safe connection to 3.6 V signals even when powered at 0.8 V, eliminating external clamping diodes.
Operating Temperature –40 °C to +125 °C - qualified for under-hood automotive, industrial control, and extended-range IoT edge nodes.
VIL/VIH Thresholds VIL ≤ 0.35×VCC, VIH ≥ 0.65×VCC (typ.) - provides >30% noise margin at 1.8 V and >55% at 3.3 V supply.

Pinout & Package

TSSOP5 plastic thin shrink small outline package (SOT353-1), 5-lead, body width 1.25 mm, 0.65 mm pitch, exposed pad not present.

Pin/Terminal Circuit Role Design Meaning
1 B Second logic input; Schmitt-triggered for noise rejection and monotonic switching.
2 A Primary logic input; electrically identical to Pin 1, supports same voltage and timing specs.
3 GND Digital ground reference; must be low-impedance connection to minimize ground bounce in high-speed switching.
4 Y OR output; drives capacitive loads up to 30 pF with sub-5 ns delay at 3.3 V; open-drain capable only with external pull-up.
5 VCC Power supply input; decoupling capacitor (100 nF) recommended within 5 mm of this pin for stable high-speed operation.

Key Features

Feature Design Value
Wide VCC range 0.8 V to 3.6 V operation - eliminates need for separate voltage translators in multi-rail embedded systems.
IOFF partial power-down Output disabled with VCC = 0 V; leakage < ±0.75 µA - enables safe insertion/removal in live backplanes or modular subsystems.
Schmitt-trigger inputs Hysteresis ≥ 0.15×VCC - rejects EMI-induced glitches on long PCB traces or unshielded cables in industrial environments.
Low dynamic power CPD = 3.9 pF at 3.3 V - reduces switching power to < 43 µW at 1 MHz with 15 pF load, critical for energy harvesting designs.
ESD robustness HBM > 5000 V, CDM > 1000 V - withstands handling and board-level assembly without additional protection circuitry.

Applications

Industrial Sensor Interface Portable Medical Monitor

Use Scenario: Aggregating fault signals from multiple temperature, pressure, and flow sensors into a single alert line feeding a microcontroller interrupt pin.

IC Role / Device Role / Timing Role: Single OR gate performing wired-OR alarm consolidation; Schmitt inputs tolerate slow RC-filtered sensor outputs.

Use Value: Eliminates need for software polling or extra GPIOs; IOFF prevents backfeed when MCU is asleep and VCC is partially powered.

Use Scenario: Enabling wake-on-event logic in a wearable ECG patch that monitors lead-off detection and battery low alerts.

IC Role / Device Role / Timing Role: OR gate combining two asynchronous low-power comparator outputs to trigger system wake-up via single interrupt line.

Use Value: Sub-1 µA static current extends battery life beyond 3 months; 0.8 V operation matches coin-cell discharge curve.

Automotive Body Control Module Smart Home Hub Logic

Use Scenario: Detecting any door-open condition across four doors using discrete switch inputs routed to a central controller.

IC Role / Device Role / Timing Role: Input conditioning and OR summation before CAN transceiver input; operates across –40 °C to +125 °C ambient.

Use Value: Guaranteed timing at 125 °C avoids false alarms due to thermal drift; overvoltage-tolerant inputs survive load-dump transients.

Use Scenario: Combining occupancy sensor, PIR motion, and manual override switch signals to enable lighting control logic in a Zigbee-enabled hub.

IC Role / Device Role / Timing Role: Low-voltage OR gate interfacing 1.8 V sensors and 3.3 V MCU GPIOs without level-shifting components.

Use Value: Dual-voltage compatibility reduces BOM count; 3.6 V input tolerance allows direct connection to 3.3 V rail-sensing comparators.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC1G32DBVR Wider VCC range (1.65–5.5 V); no Schmitt inputs; higher ICC (10 µA typ); no IOFF. Requires external clamping for 3.6 V inputs at 1.8 V VCC; unsuitable for partial power-down systems. Select when interfacing legacy 5 V peripherals or where Schmitt noise immunity is unnecessary.
74LVC1G32GW,125 Same TSSOP5 package; VCC = 1.65–5.5 V; no IOFF; VIH/VIL fixed thresholds (not ratio-based); tpd ~3.7 ns @ 3.3 V. Lacks voltage-scaling input thresholds and power-down isolation - incompatible with sub-1.65 V operation or hot-swap use cases. Choose only if design uses ≥1.65 V supply and does not require zero-power isolation during standby.

Compared with SN74LVC1G32DBVR and 74LVC1G32GW,125, the 74AUP1G32GW,125 uniquely supports 0.8 V operation, Schmitt-trigger noise rejection, and IOFF-enabled partial power-down - making it the sole option for ultra-low-voltage, mixed-rail, or fail-safe hot-swap logic interfacing.

Availability

74AUP1G32GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical monitors, automotive body control modules, and smart home hubs requiring stable component supply across extended temperature ranges and low-power constraints.

Supply support for 74AUP1G32GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications demanding sub-1 µA static current, wide VCC scalability, and robust IO behavior - designed specifically for next-generation IoT endpoints and automotive domain controllers.

FAQ

Does 74AUP1G32GW,125 support true bidirectional signal routing?

No. The 74AUP1G32GW,125 is a unidirectional OR gate with defined inputs (A, B) and output (Y). It lacks internal pass-gate architecture or direction-control logic. Its IOFF feature only disables the output driver during power-down - it does not enable reverse signal flow or bus-sharing capability.

Can Pin 5 (VCC) be left floating while using IOFF mode?

No. VCC must be connected to a defined voltage (including 0 V) for IOFF to function correctly. When VCC = 0 V, the IOFF circuit actively disables the output stage. Floating VCC violates Absolute Maximum Ratings and may cause undefined output states, increased leakage, or latch-up risk per JEDEC JESD78 Class II Level B compliance.

What is the maximum capacitive load this device can drive reliably at 3.3 V?

The device is characterized up to 30 pF load capacitance, with tpd ≤ 6.4 ns and VOL ≤ 0.44 V at IO = 4.0 mA. Driving >30 pF risks violating setup/hold timing in synchronous systems and may increase overshoot beyond the specified <10% of VCC limit - external series termination or buffer staging is recommended beyond this value.

Is the Schmitt-trigger hysteresis adjustable or fixed?

Hysteresis is fixed and process-defined, with typical ΔV = VIH − VIL ≈ 0.3×VCC across the full 0.8–3.6 V range. No external components or configuration pins modify it. Data sheet Table 7 confirms minimum hysteresis of 0.15×VCC at all temperatures and supply voltages, ensuring consistent noise margin without user tuning.

74AUP1G32GW,125 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
5-TSSOP, SC-70-5, SOT-353
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
OR Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
-
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
4mA, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
6.4ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
5-TSSOP

74AUP1G32GW,125 FAQ

1.How can I place an order for 74AUP1G32GW,125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G32GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1G32GW,125 reliable?

The price and inventory of 74AUP1G32GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G32GW,125 is usually 5 days.

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5.How can I obtain technical support or documentation for 74AUP1G32GW,125?

For technical support, including 74AUP1G32GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G32GW,125 requirements.

6.How does Aetrix verify that 74AUP1G32GW,125 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G32GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G32GW,125 meets industry standards.

7.What is the process for return or replacement of 74AUP1G32GW,125?

All 74AUP1G32GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G32GW,125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G32GW,125 part is unused and in its original packaging.

Return procedure for 74AUP1G32GW,125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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