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NXP Semiconductors 74AUP1G32GW/DG,125
- Part No.:
- 74AUP1G32GW/DG,125
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G32GW/DG,125.pdf
- Description:
- IC GATE OR 1CH 2-INP 5TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,390
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Product details
Overview
74AUP1G32GW/DG,125 from Nexperia is a single 2-input CMOS OR gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤0.9 µA), propagation delay as low as 0.9 ns at 3.6 V, and IOFF-enabled partial power-down protection. It is used in battery-powered sensor interfaces and level-shifting logic blocks where noise immunity and rail-to-rail compatibility are critical.
For engineers reviewing the 74AUP1G32GW/DG,125 datasheet, 74AUP1G32GW/DG,125 pinout, 74AUP1G32GW/DG,125 application, or 74AUP1G32GW/DG,125 equivalent, key selection criteria include its 5-pin TSSOP5 package, −40 °C to +125 °C temperature rating, Schmitt-trigger input hysteresis, IOFF leakage control, and guaranteed operation down to 0.8 V.
Technical Context
This device implements a single 2-input positive-logic OR function with Schmitt-trigger inputs that tolerate slow-rising/falling signals and provide high noise immunity. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
The logic core is optimized for ultra-low dynamic power via sub-4 pF CPD and supports load capacitances up to 30 pF while maintaining propagation delays under 4.6 ns across the full industrial temperature range and supply voltage span.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - enables direct interfacing with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max Propagation Delay | 4.6 ns at VCC = 3.6 V, CL = 5 pF, −40 °C to +125 °C - ensures timing-critical signal combining in real-time control paths. |
| Static Supply Current | ≤0.9 µA at VCC = 0.8–3.6 V - extends battery life in always-on IoT edge nodes and wearable sensors. |
| IOFF Leakage | ±0.75 µA at VCC = 0 V - prevents destructive back-current in multi-rail systems during partial power-down sequences. |
| Input Hysteresis | Typical ΔV = 0.1 × VCC - rejects EMI and contact bounce in mechanical switch debouncing applications. |
| ESD Rating | HBM >5000 V, CDM >1000 V - sustains handling and board-level integration without additional protection circuitry. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | B | Second logic input; Schmitt-triggered for noise rejection on slow or noisy signals. |
| 2 | A | Primary logic input; identical electrical behavior to Pin 1, fully interchangeable. |
| 3 | GND | Ground reference for all internal circuitry and I/O; must be low-impedance for stable noise margin. |
| 4 | Y | OR output; drives capacitive loads up to 30 pF with guaranteed VOL ≤ 0.5 V at 4 mA sink. |
| 5 | VCC | Power supply input; supports decoupling directly at pin for minimal switching noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable operation with slow edges (e.g., RC-filtered sensor outputs or mechanical switches) without external hysteresis components. |
| IOFF partial power-down | Prevents back-current flow when VCC = 0 V, allowing safe hot-insertion or independent domain shutdown in mixed-voltage systems. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting - simplifies interface to higher-voltage peripherals without clamping diodes. |
| Ultra-low dynamic power | CPD = 3.9 pF at 3.6 V enables <1 µW dynamic power at 1 MHz toggle rate - ideal for energy-constrained microcontroller GPIO expansion. |
| −40 °C to +125 °C operation | Qualified for automotive under-hood, industrial motor drives, and outdoor infrastructure deployments without derating. |
Applications
| Industrial Sensor Interface | Low-Power Wearable Logic |
|---|---|
Use Scenario: Combining fault signals from multiple temperature, pressure, and vibration sensors in a PLC I/O module. IC Role / Device Role / Timing Role: Single OR gate aggregates active-high fault flags; Schmitt inputs reject EMI from adjacent motor drives. Use Value: Eliminates need for discrete pull-up resistors and RC filters while ensuring deterministic response under 5 ns at 3.3 V. | Use Scenario: Debouncing tactile buttons and wake-on-event logic in a hearable device powered by a 1.2 V coin cell. IC Role / Device Role / Timing Role: Input conditioning block converting mechanical switch bounce into clean digital pulses for MCU interrupt input. Use Value: Reduces system standby current to <1 µA via IOFF and enables direct 1.2 V operation without LDO overhead. |
| Multi-Rail Power Sequencing | Level-Shifted GPIO Expansion |
Use Scenario: Enabling a 3.3 V subsystem only after both 1.8 V and 2.5 V rails are stable in an FPGA-based embedded vision camera. IC Role / Device Role / Timing Role: OR gate monitors two independent power-good signals; IOFF prevents reverse current if one rail powers down first. Use Value: Guarantees safe sequencing without external MOSFETs or complex supervisor ICs. | Use Scenario: Extending GPIO count of a 0.8 V AI accelerator SoC to drive 1.8 V status LEDs and 3.3 V communication enable lines. IC Role / Device Role / Timing Role: Bidirectional voltage translation element leveraging overvoltage-tolerant inputs and rail-flexible output swing. Use Value: Achieves level shifting without dedicated translators - reduces BOM count and layout area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G32DBVR | Higher ICC (max 10 µA), no Schmitt inputs, 1.65–5.5 V supply range, SOT-23-5 package. | Lacks input hysteresis and ultra-low-power capability; suitable only where noise immunity is non-critical and supply >1.65 V. | Select when cost sensitivity outweighs noise robustness and sub-µA standby requirements. |
| 74LVC1G32GV,125 | Same TSSOP5 package, but lacks IOFF and Schmitt inputs; max ICC = 4 µA; rated −40 °C to +125 °C. | Cannot support partial power-down; requires external clamping for overvoltage inputs above VCC. | Choose only for legacy designs already using LVC family and where IOFF/Schmitt are unused. |
Compared with SN74LVC1G32DBVR and 74LVC1G32GV,125, the 74AUP1G32GW/DG,125 delivers superior noise immunity, 10× lower static current, and safe multi-rail interoperability - making it the optimal choice for next-generation ultra-low-power and automotive-grade logic interfaces.
Availability
74AUP1G32GW/DG,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered wearables, multi-rail power sequencers, and level-shifted GPIO expansion requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1G32GW/DG,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading global semiconductor expert in discrete, logic, and MOSFET devices, headquartered in Nijmegen, Netherlands, with manufacturing in Europe and Asia.
The 74AUP (Advanced Ultra-low Power) product line targets energy-sensitive applications including portable electronics, automotive body control, and industrial IoT, emphasizing sub-1 µA quiescent current and wide-VCC operation without performance trade-offs.
FAQ
What is the maximum operating temperature for the 74AUP1G32GW/DG,125?
The 74AUP1G32GW/DG,125 is fully specified from −40 °C to +125 °C ambient temperature. This rating is validated per JEDEC JESD22-A108 and applies across the full 0.8 V to 3.6 V supply range, making it suitable for under-hood automotive and industrial motor-control environments where thermal margins are constrained.
Does the 74AUP1G32GW/DG,125 support partial power-down mode?
Yes, the 74AUP1G32GW/DG,125 integrates IOFF circuitry that disables the output stage when VCC = 0 V, limiting power-off leakage to ±0.75 µA. This feature prevents damaging back-current flow in multi-supply systems - for example, when interfacing with a powered 3.3 V bus while the local 1.8 V rail is off - and is explicitly verified in Table 7 of the datasheet.
Can the 74AUP1G32GW/DG,125 accept input voltages higher than its VCC supply?
Yes, the 74AUP1G32GW/DG,125 features overvoltage-tolerant inputs rated to 3.6 V regardless of VCC setting (0.8 V to 3.6 V). This allows direct connection to higher-voltage peripherals - such as 3.3 V sensors or microcontrollers - without external clamping diodes or level shifters, as confirmed in Section 2 and Table 5 of the datasheet.
What is the typical propagation delay of the 74AUP1G32GW/DG,125 at 1.8 V supply?
At VCC = 1.8 V, Tamb = 25 °C, and CL = 5 pF, the typical propagation delay (tpd) of the 74AUP1G32GW/DG,125 is 3.0 ns (Table 8). Over the full −40 °C to +125 °C range, tpd remains ≤5.2 ns under identical conditions, enabling reliable timing in 1.8 V FPGA I/O banks and low-voltage microcontroller subsystems.
Is the 74AUP1G32GW/DG,125 pin-compatible with other 74AUP1Gxx variants in TSSOP5?
No - the 74AUP1G32GW/DG,125 uses a fixed 5-pin TSSOP5 (SOT353-1) pinout (A, B, GND, Y, VCC), but other 74AUP1Gxx functions (e.g., inverters, AND gates) share this same physical layout only if explicitly designated as pin-compatible in their respective datasheets. Always verify pin mapping per device; do not assume functional interchangeability based on package alone.
74AUP1G32GW/DG,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.4ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G32GW/DG,125 FAQ
1.How can I place an order for 74AUP1G32GW/DG,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G32GW/DG,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G32GW/DG,125 reliable?
The price and inventory of 74AUP1G32GW/DG,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G32GW/DG,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G32GW/DG,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G32GW/DG,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G32GW/DG,125?
74AUP1G32GW/DG,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G32GW/DG,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G32GW/DG,125?
For technical support, including 74AUP1G32GW/DG,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G32GW/DG,125 requirements.
6.How does Aetrix verify that 74AUP1G32GW/DG,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G32GW/DG,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G32GW/DG,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G32GW/DG,125?
All 74AUP1G32GW/DG,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G32GW/DG,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G32GW/DG,125 part is unused and in its original packaging.
Return procedure for 74AUP1G32GW/DG,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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