NXP Semiconductors 74AUP1G332GN,132
- Part No.:
- 74AUP1G332GN,132
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G332GN,132.pdf
- Description:
- IC GATE OR 1CH 3-INP 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:100,000
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Product details
Overview
74AUP1G332GN,132 from Nexperia is a single 3-input OR gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 1.1 ns at 3.0 V with 5 pF load - deployed in battery-powered sensor interfaces and low-voltage logic translation stages.
For engineers reviewing the 74AUP1G332GN,132 datasheet, 74AUP1G332GN,132 pinout, 74AUP1G332GN,132 application, or 74AUP1G332GN,132 equivalent, this device serves as a drop-in logic-level combiner where input noise immunity, sub-1-μA quiescent draw, and guaranteed operation down to 0.8 V are critical selection criteria.
Technical Context
This device implements a standard positive-logic 3-input OR function (Y = A + B + C) with Schmitt-trigger hysteresis on all inputs, enabling robust operation with slow-rising signals (Δt/ΔV ≤ 200 ns/V). Its IOFF circuit actively disables output terminals when VCC = 0 V, blocking backflow current during partial system power-down.
Designed for wide-VCC compatibility, it meets JEDEC standards JESD8-12 through JESD8C across five voltage bands and guarantees latch-up immunity >100 mA per JESD78 Class II. Input overvoltage tolerance up to 3.6 V allows interfacing with higher-voltage domains without level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | 3-input OR gate (Y = A ∨ B ∨ C); Schmitt-trigger inputs ensure noise margin ≥0.3×VCC at 1.65 V–1.95 V |
| Supply Voltage Range | 0.8 V to 3.6 V; supports direct integration into 1.2 V, 1.8 V, 2.5 V, and 3.3 V subsystems |
| Max ICC (Quiescent) | 1.4 μA at −40 °C to +125 °C; enables multi-year battery life in always-on IoT endpoints |
| Propagation Delay | 1.1 ns (min) at VCC = 3.0 V, CL = 5 pF; ensures timing-critical signal combining in high-speed control paths |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V; prevents destructive backfeed current during hot-swap or partial shutdown |
| Input Hysteresis | Typical 100 mV at VCC = 1.2 V; rejects EMI-induced glitches on long PCB traces or flex cables |
| ESD Rating | HBM >5000 V, CDM >1000 V; survives handling and board assembly without external protection |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal footprint (0.9 × 1.0 × 0.35 mm body), optimized for space-constrained wearables and portable medical devices.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data input A | Schmitt-triggered; accepts 0 V to 3.6 V regardless of VCC; tolerant of slow edges |
| 2 (GND) | Ground reference | 0 V return path for all internal logic and I/O; must be low-impedance for noise immunity |
| 3 (B) | Data input B | Identical electrical behavior to Pin 1; enables 3-input OR combination without external gates |
| 4 (Y) | Output Y | CMOS push-pull; drives loads up to ±4 mA at 3.0 V; IOFF disables output when VCC = 0 V |
| 5 (VCC) | Supply voltage | Primary power rail; powers internal logic and output stage; IOFF activation tied to this pin |
| 6 (C) | Data input C | Third OR input; shares same hysteresis and voltage tolerance as Pins 1 and 3 |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (0.8 V–3.6 V) | Eliminates need for separate level translators in mixed-voltage systems (e.g., 1.2 V MCU + 3.3 V sensor) |
| Schmitt-trigger inputs | Provides ≥100 mV hysteresis at 1.2 V, rejecting noise on unshielded interconnects in industrial sensors |
| IOFF partial power-down | Blocks bidirectional current flow when VCC = 0 V, enabling safe hot-plug of peripheral logic blocks |
| Low dynamic power (CPD = 4.0 pF) | Reduces switching power to <1 μW at 1 MHz, critical for duty-cycled wireless transceivers |
| −40 °C to +125 °C operation | Validated for under-hood automotive modules and outdoor edge AI accelerators without derating |
Applications
| Industrial Sensor Hub | Portable Medical Monitor |
|---|---|
|
Use Scenario: Combining fault alerts from three independent temperature, pressure, and humidity sensors before triggering MCU interrupt. IC Role / Device Role / Timing Role: Single-point OR logic aggregator with Schmitt inputs rejecting trace noise on 10 cm sensor harnesses. Use Value: Reduces BOM count by eliminating discrete diode-OR or additional gate ICs while maintaining <2 ns timing skew. |
Use Scenario: Enabling low-power wake-up of ECG front-end ASIC when any of three patient-contact electrodes detects valid contact. IC Role / Device Role / Timing Role: Always-on combiner driving enable line to ASIC; operates at 0.9 V to minimize battery drain. Use Value: Achieves 0.9 μA total system standby current with guaranteed detection latency <100 ns at 0.9 V. |
| Automotive Body Control Module | IoT Edge Gateway |
|
Use Scenario: Merging door-open, trunk-open, and hood-open signals to activate interior lighting driver only when any panel is unlatched. IC Role / Device Role / Timing Role: Fault-tolerant OR gate with IOFF; isolated from main 12 V rail during sleep mode via local LDO. Use Value: Prevents backfeed into powered-down microcontroller I/O pins, eliminating risk of latch-up during key-off state. |
Use Scenario: Consolidating status flags from BLE, LoRa, and Wi-Fi radio subsystems to indicate "any radio active" for thermal management. IC Role / Device Role / Timing Role: Voltage-scalable logic combiner interfacing 1.8 V radios and 3.3 V thermal controller. Use Value: Enables unified thermal throttling decision without voltage translation, reducing layout area by 1.2 mm². |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G332DBVR | Higher ICC (max 10 μA), no Schmitt inputs, 1.65 V–5.5 V VCC range | Lacks noise immunity on slow signals; requires clean input edges | Select when interfacing with fast CMOS drivers and full 5 V compatibility is required |
| 74LVC1G32GV,125 | 2-input OR only; identical package (SOT1115), same VCC range and IOFF | Requires external wiring or second gate to implement 3-input function | Choose only if design already uses this part and board space allows cascading |
Compared with SN74LVC1G332DBVR and 74LVC1G32GV,125, the 74AUP1G332GN,132 uniquely delivers Schmitt-trigger noise rejection, sub-1.5 μA quiescent draw, and guaranteed 0.8 V operation - making it the sole choice for ultra-low-power, noise-prone, or sub-1 V logic domains.
Availability
74AUP1G332GN,132 is available at Aetrix Electronics and suitable for industrial sensor hubs, portable medical monitors, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G332GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions for automotive, industrial, and mobile markets.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, emphasizing minimal static/dynamic power, wide voltage scalability, and robustness in noisy environments.
FAQ
Does the 74AUP1G332GN,132 support true 0.8 V logic operation with guaranteed timing?
Yes. The datasheet specifies propagation delay (tpd) down to 1.9 ns at VCC = 0.8 V with CL = 5 pF and defines VIH/VIL thresholds scaled to VCC (e.g., VIH = 0.70 × VCC min at −40 °C to +125 °C), ensuring functional correctness and timing predictability at 0.8 V.
Can the IOFF feature be used to isolate this gate between two independently powered voltage domains?
No. IOFF only disables the output when VCC = 0 V - it does not provide bidirectional isolation between differing VCC rails. For domain isolation, a dedicated level translator or bus switch is required; this device assumes shared ground and single-supply operation.
What is the maximum capacitive load this device can drive while maintaining specified tpd?
The datasheet characterizes tpd up to CL = 30 pF across all VCC ranges. At VCC = 3.0 V, tpd remains ≤6.7 ns (max) with 30 pF load. Driving >30 pF will increase delay nonlinearly and may violate setup/hold margins in synchronous systems.
Is the SOT1115 (XSON6) package of 74AUP1G332GN,132 compatible with standard reflow profiles for lead-free assembly?
Yes. Nexperia qualifies SOT1115 for IPC/JEDEC J-STD-020D moisture sensitivity level 1 (MSL1) and specifies peak reflow temperature of 260 °C for 30 seconds, fully compatible with standard Pb-free soldering processes used in high-reliability industrial manufacturing.
74AUP1G332GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 5.5ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AUP1G332GN,132 FAQ
1.How can I place an order for 74AUP1G332GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G332GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G332GN,132 reliable?
The price and inventory of 74AUP1G332GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G332GN,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1G332GN,132?
For technical support, including 74AUP1G332GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G332GN,132 requirements.
6.How does Aetrix verify that 74AUP1G332GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G332GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G332GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G332GN,132?
All 74AUP1G332GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G332GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G332GN,132 part is unused and in its original packaging.
Return procedure for 74AUP1G332GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G332GN,132 Tags
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