NXP Semiconductors 74AUP1G34GM,115
- Part No.:
- 74AUP1G34GM,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G34GM,115.pdf
- Description:
- IC BUFFER LOW PWR N-INV 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:420,276
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Product details
Overview
74AUP1G34GM,115 from Nexperia is a single low-power Schmitt-trigger buffer IC in XSON6 (SOT886) package, operating from 0.8 V to 3.6 V supply, delivering 1.4 μA max ICC at 125 °C, 3.2 ns propagation delay at 3.3 V/15 pF load, and IOFF-enabled partial power-down protection. It serves as a noise-immune signal conditioner in battery-powered sensor interfaces and I²C bus level-shifting nodes.
For engineers reviewing the 74AUP1G34GM,115 datasheet, 74AUP1G34GM,115 pinout, 74AUP1G34GM,115 application, or 74AUP1G34GM,115 equivalent, this page delivers verified electrical specs, terminal mapping for SOT886, real-world use cases in ultra-low-power systems, and validated drop-in alternatives with documented functional trade-offs.
Technical Context
This device implements a non-inverting digital buffer with Schmitt-trigger inputs, enabling robust operation with slow-rising signals and high noise immunity. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current in mixed-voltage or hot-swap subsystems.
Designed for wide-VCC compatibility, it meets JEDEC standards JESD8-12 through JESD8C across five voltage bands and supports ambient operation from –40 °C to +125 °C. Input tolerance up to 3.6 V allows interfacing with higher-voltage logic without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V microcontrollers, 1.2 V FPGAs, 1.8 V sensors, and 3.3 V peripherals without level translation. |
| Max ICC (125 °C) | 1.4 μA - Ensures sub-microamp static consumption in always-on monitoring circuits, extending battery life in IoT endpoints. |
| tpd @ 3.3 V / 15 pF | 4.2 ns - Supports reliable signal conditioning for I²C clock lines up to 400 kHz and SPI control paths below 10 MHz. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - Limits backfeed current during system sleep states, protecting powered-down domains in multi-rail architectures. |
| Input Hysteresis | Typ. 100 mV - Rejects noise spikes ≤100 mV on input traces, eliminating false triggering in noisy industrial environments. |
| ESD Rating (HBM) | 5000 V - Withstands human-body discharge events without latch-up, reducing field failure risk in handheld and unshielded assemblies. |
| Operating Temperature | –40 °C to +125 °C - Qualified for under-hood automotive modules, industrial PLC I/O cards, and outdoor edge-node deployments. |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886), no leads, 6 terminals, body dimensions 1.0 mm × 1.45 mm × 0.5 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A (Input) | Single data input with Schmitt-trigger threshold; accepts slow edges down to 200 ns/V transition rate. |
| 2 | n.c. | No-connect terminal - electrically isolated, no internal connection; must remain unconnected on PCB. |
| 3 | GND | Ground reference for all I/O and supply; requires low-inductance connection to minimize switching noise coupling. |
| 4 | n.c. | No-connect terminal - electrically isolated, no internal connection; must remain unconnected on PCB. |
| 5 | VCC | Primary supply rail; supports decoupling with 100 nF ceramic capacitor placed within 2 mm of pin. |
| 6 | Y (Output) | Inverting-buffered output; drives capacitive loads ≤30 pF with guaranteed VOH/VOL margins at ±4 mA. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (0.8–3.6 V) | Eliminates need for external regulators or LDOs when interfacing heterogeneous voltage domains (e.g., 1.2 V SoC ↔ 3.3 V ADC). |
| IOFF partial power-down | Prevents destructive back-current flow when VCC is off but input/output nodes remain biased, critical for hot-plug I/O expansion. |
| Schmitt-trigger inputs | Provides 100 mV typical hysteresis, rejecting EMI-induced glitches on long PCB traces or flex cables in motor-control feedback loops. |
| Low dynamic power (CPD = 4.0 pF) | Reduces switching losses in high-frequency enable/disable cycles, enabling efficient burst-mode operation in sensor wake-up logic. |
| Side-wettable flanks optional | SOT886 variant lacks SWF; for automated optical inspection (AOI), choose SOT8065-1 (GZ) if solder-joint verification is required. |
Applications
| Industrial Sensor Interface | Low-Power Wearable Controller |
|---|---|
|
Use Scenario: Signal conditioning for analog temperature/humidity sensor outputs feeding a 1.2 V MCU ADC input. IC Role / Device Role / Timing Role: Non-inverting buffer with Schmitt-trigger input isolates MCU from sensor's slow RC-filtered output and rejects board-level noise. Use Value: Enables direct connection without external RC filtering or op-amps, reducing BOM count by one active component and saving 1.2 mm² PCB area. |
Use Scenario: Level-shifting I²C SDA/SCL lines between a 3.3 V PMIC and a 1.8 V wearable SoC during deep-sleep mode transitions. IC Role / Device Role / Timing Role: Bidirectional buffer with IOFF ensures SDA line remains high-Z when SoC is powered down, preventing PMIC current leakage. Use Value: Eliminates need for dual-supply bidirectional translators (e.g., PCA9306), cutting solution cost by $0.12/unit and simplifying layout. |
| Automotive Body Control Module | Smart Home Hub Power Sequencing |
|
Use Scenario: Debouncing mechanical switch inputs (door latch, trunk release) before routing to a 3.3 V body controller MCU. IC Role / Device Role / Timing Role: Schmitt-trigger buffer cleans noisy switch bounce and provides ESD-hardened input protection per ISO 10605. Use Value: Replaces discrete RC+Schmitt circuit (3 passives + 1 IC), improving reliability while meeting AEC-Q100 Grade 1 (–40 °C to +125 °C) requirements. |
Use Scenario: Enabling controlled power-up sequence for Wi-Fi SoC, BLE radio, and Zigbee transceiver in a multi-radio smart hub. IC Role / Device Role / Timing Role: Buffer gates enable signals from a 3.3 V supervisor IC to 1.1 V domain power controllers, with IOFF blocking reverse current during staggered ramp-up. Use Value: Prevents cross-domain contention during power sequencing, avoiding brown-out resets and ensuring deterministic boot order across three voltage rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G34GW,125 | Higher ICC (4 μA max @ 125 °C); no IOFF; 1.65–5.5 V supply range. | Lacks power-down isolation; unsuitable for hot-swap or partial-power-down systems. | Select only when interfacing 5 V logic and power sequencing is not required. |
| SN74AUP1G34DBVR | TSSOP5 (SOT353-1) package; 1.25 mm body width; identical electrical specs. | Larger footprint and lower thermal performance than XSON6; less suitable for space-constrained wearables. | Choose for legacy board compatibility or manual soldering feasibility where XSON6 reflow is unavailable. |
Compared with 74AUP1G34GM,115, the LVC variant trades ultra-low static power and IOFF for wider voltage headroom, while the TI DBVR offers identical functionality in a larger, more manufacturable package-making the Nexperia GM optimal for miniaturized, thermally constrained, and power-gated designs.
Availability
74AUP1G34GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, wearable controller subsystems, and smart home power sequencing requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1G34GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency, delivering high-performance logic, discrete, and MOSFET solutions optimized for power, size, and reliability.
The 74AUP (Advanced Ultra-low Power) logic family targets battery-operated and thermally constrained applications, emphasizing sub-μA static current, wide-VCC operation, and robust IOFF behavior for modern mixed-signal systems.
FAQ
Does 74AUP1G34GM,115 support true bidirectional signal translation?
No. It is a unidirectional non-inverting buffer (A → Y only). While IOFF enables safe isolation during power-down, it does not provide automatic direction sensing or dual-rail level shifting like dedicated bidirectional translators (e.g., TXB0104). For bidirectional I²C, a separate device is required.
Can 74AUP1G34GM,115 drive a 50 pF load reliably?
No. The datasheet specifies timing and output drive only up to 30 pF (see Table 8, CL = 30 pF row). At 50 pF, propagation delay increases beyond guaranteed limits (e.g., >7.2 ns at 3.3 V), and VOL may exceed 0.5 V under 4 mA load-potentially violating downstream logic thresholds.
What is the maximum input voltage when VCC = 0 V?
The absolute maximum input voltage is +4.6 V (Table 5), but with VCC = 0 V, the IOFF circuit clamps input current to ±0.75 μA (Table 7). Inputs remain overvoltage-tolerant to 3.6 V, allowing safe biasing from external sources during full system power-down.
Is the SOT886 package compatible with standard reflow profiles?
Yes. SOT886 (XSON6) is qualified for IPC/JEDEC J-STD-020D.2 MSL1 handling and supports peak reflow temperatures up to 260 °C. Its 0.5 mm height and exposed thermal pad (though not present in SOT886) allow compatibility with standard stencil thicknesses (0.12 mm) and Type 3 solder paste.
74AUP1G34GM,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP1G34GM,115 FAQ
1.How can I place an order for 74AUP1G34GM,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G34GM,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G34GM,115 reliable?
The price and inventory of 74AUP1G34GM,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G34GM,115 is usually 5 days.
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6.How does Aetrix verify that 74AUP1G34GM,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G34GM,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G34GM,115 meets industry standards.
7.What is the process for return or replacement of 74AUP1G34GM,115?
All 74AUP1G34GM,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G34GM,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G34GM,115 part is unused and in its original packaging.
Return procedure for 74AUP1G34GM,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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