NXP Semiconductors 74AUP1G34GN,132
- Part No.:
- 74AUP1G34GN,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G34GN,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
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Product details
Overview
74AUP1G34GN,132 from Nexperia is a single low-power CMOS buffer with Schmitt-trigger input, designed for signal conditioning in ultra-low-voltage digital systems. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 25 °C, supports -40 °C to +125 °C ambient, and features IOFF partial power-down protection. It is used in battery-powered sensor interfaces where input noise immunity and rail-to-rail compatibility are critical.
For engineers reviewing the 74AUP1G34GN,132 datasheet, 74AUP1G34GN,132 pinout, 74AUP1G34GN,132 application, or 74AUP1G34GN,132 equivalent, this device is selected for its sub-1 μA static current, 0.9 × 1.0 × 0.35 mm XSON6 package (SOT1115), Schmitt-trigger hysteresis, and guaranteed operation down to 0.8 V - key parameters for energy-constrained IoT node design and level-shifting in mixed-supply subsystems.
Technical Context
This buffer implements a non-inverting logic function (A → Y) with hysteresis on the input to tolerate slow-rising signals and reject high-frequency noise. Its IOFF circuit actively disables output leakage when VCC = 0 V, enabling safe hot-insertion in multi-rail systems without backfeed current.
It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands and meets ANSI/ESDA/JEDEC JS-001 Class 3A (≥5000 V HBM) and JS-002 Class C3 (≥1000 V CDM) ESD ratings - confirming robustness in automated assembly and field-deployed edge devices.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interface with 0.9 V logic families and compatibility with 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains. |
| Max ICC (Static) | 0.9 μA at 25 °C - ensures negligible quiescent drain in always-on sensor wake-up circuits. |
| Input Hysteresis | Schmitt-trigger action - provides ≥100 mV typical hysteresis at 1.8 V, rejecting noise on long PCB traces or unshielded cables. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - prevents damaging backflow current during partial system power-down. |
| Propagation Delay | 1.4 ns min / 4.2 ns max at VCC = 3.3 V, CL = 15 pF - supports timing-critical signal buffering up to ~100 MHz toggle rates. |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules and industrial control enclosures. |
| ESD Rating (HBM) | ≥5000 V - eliminates need for external transient protection in handheld and portable equipment. |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 6 terminals, body size 0.9 mm × 1.0 mm × 0.35 mm, thermal pad not present, side-wettable flanks absent.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A (Input) | Data input with Schmitt-trigger threshold; accepts overvoltage up to 3.6 V regardless of VCC. |
| 2 | n.c. | No connection - electrically isolated; no internal bond wire or die attachment. |
| 3 | GND | Ground reference for all I/O and internal logic; must be low-impedance for stable noise immunity. |
| 4 | n.c. | No connection - electrically isolated; no internal bond wire or die attachment. |
| 5 | Y (Output) | Push-pull CMOS output; drives loads up to ±20 mA; supports rail-to-rail swing. |
| 6 | VCC | Power supply input; IOFF activation occurs when VCC drops below 0.2 V, disabling output state. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 0.9 μA max across full VCC range - extends battery life in coin-cell-powered wearables. |
| IOFF partial power-down | Active output disable at VCC = 0 V - enables safe integration into PCIe-style hot-plug architectures. |
| Overvoltage-tolerant inputs | VI up to 3.6 V independent of VCC - allows interfacing with higher-voltage peripherals without level shifters. |
| High noise immunity | Input hysteresis ≥100 mV at 1.8 V - suppresses false triggering from EMI in motor-drive proximity sensors. |
| JEDEC-compliant voltage bands | Validated per JESD8-12, JESD8-11, JESD8-7, JESD8-5, JESD8C - ensures interoperability across global semiconductor supply chains. |
Applications
| Industrial Sensor Interface | Low-Power Wearable Data Path |
|---|---|
|
Use Scenario: Signal conditioning for analog sensor outputs digitized by ultra-low-power ADCs in factory-floor vibration monitors. IC Role / Device Role / Timing Role: Buffering and noise filtering of slow-rising comparator outputs before microcontroller GPIO sampling. Use Value: Schmitt-trigger input rejects 50/60 Hz line noise and contact bounce; 0.8 V operation matches energy-harvesting PMIC output rails. |
Use Scenario: Level translation between a 1.1 V BLE SoC and a 1.8 V environmental sensor in a medical patch. IC Role / Device Role / Timing Role: Unidirectional voltage-domain bridging with zero static current draw during sleep mode. Use Value: IOFF prevents backfeed into the SoC's powered-down I/O domain; 0.35 mm height fits within 1.0 mm total stack height budget. |
| Automotive Body Control Module | Smart Home Edge Node |
|
Use Scenario: Debouncing mechanical switch inputs in door latch assemblies exposed to wide temperature swings. IC Role / Device Role / Timing Role: Input hysteresis and rail-to-rail output drive directly into MCU interrupt pins. Use Value: -40 °C to +125 °C qualification ensures reliability in engine bay proximity; 5000 V HBM withstands ESD events during service replacement. |
Use Scenario: Isolating GPIO lines between a 3.3 V Wi-Fi MCU and 2.5 V Zigbee transceiver in a battery-operated smart thermostat. IC Role / Device Role / Timing Role: Bidirectional signal integrity preservation during shared-bus arbitration. Use Value: Low 1.7 pF CO minimizes capacitive loading on high-speed I²C SCL/SCL lines; 3.6 V tolerant inputs accept open-drain pull-ups. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G34GW,125 | Higher ICC (max 40 μA), wider propagation delay (3.2 ns min / 7.2 ns max at 3.3 V), TSSOP5 package (1.25 mm width). | Lacks IOFF and Schmitt-trigger; requires external pull-ups for open-drain compatibility. | Select when cost sensitivity outweighs ultra-low-power needs and board space permits larger footprint. |
| SN74AUP1G34DBVR | Texas Instruments variant; identical electrical specs but different thermal derating (3.0 mW/K above 67 °C vs. 3.2 mW/K above 71 °C for GN). | Same functional behavior; RoHS compliance differs in halogen content per TI vs. Nexperia declarations. | Choose for TI-design ecosystem alignment or dual-sourcing requirements in automotive Tier-1 BOMs. |
Compared with 74LVC1G34GW,125, the 74AUP1G34GN,132 reduces static current by >97 % and adds Schmitt-trigger noise rejection; versus SN74AUP1G34DBVR, it offers tighter thermal derating margin and smaller 0.9 × 1.0 mm footprint - critical for space-constrained wearable PCBs.
Availability
74AUP1G34GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearable data paths, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1G34GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading Dutch semiconductor manufacturer specializing in high-volume logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications where sub-microamp quiescent current and compact packaging are mandatory design requirements.
FAQ
Can 74AUP1G34GN,132 operate with VCC = 0.85 V while driving a 15 pF load?
Yes. The datasheet guarantees tpd ≤ 11.0 ns and VOH ≥ 0.75 × VCC (≥0.64 V) at VCC = 0.85 V, Tamb = -40 °C to +85 °C, with CL = 15 pF. Output drive strength remains sufficient for interfacing with 0.9 V logic families under these conditions.
Does the IOFF feature activate automatically when VCC drops below a threshold?
Yes. IOFF engages when VCC falls below approximately 0.2 V, disabling the output stage and limiting VI/O leakage to ±0.75 μA maximum. No external enable signal or biasing is required - the circuitry is fully integrated and self-activating.
Is the SOT1115 (XSON6) package of 74AUP1G34GN,132 compatible with standard reflow profiles?
Yes. The SOT1115 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1) and supports peak reflow temperatures up to 260 °C. Its 0.35 mm profile allows use with standard stencil thicknesses and nitrogen-reflow processes.
What is the maximum input transition rate supported without signal integrity loss?
The device specifies Δt/ΔV ≤ 200 ns/V across VCC = 0.8 V to 3.6 V. At VCC = 1.8 V, this translates to a minimum valid rise/fall time of 360 ns - ensuring reliable recognition of slow-switching signals from mechanical switches or RC-filtered sensor outputs.
74AUP1G34GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AUP1G34GN,132 FAQ
1.How can I place an order for 74AUP1G34GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G34GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of 74AUP1G34GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G34GN,132 is usually 5 days.
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6.How does Aetrix verify that 74AUP1G34GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G34GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G34GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G34GN,132?
All 74AUP1G34GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G34GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G34GN,132 part is unused and in its original packaging.
Return procedure for 74AUP1G34GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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